PCB Copper Foils: A Complete Guide to Roughness, Skin Depth and Loss

PCB copper foils are usually selected by weight — half an ounce, one ounce, two ounces — as though the foil were a resistor with a thickness. At the frequencies where foil choice actually matters it is not. At 10 GHz the current in a 35 µm foil occupies about 0.65 µm of it, less than two per cent of the metal, and what decides the loss is how rough the surface is at the dielectric interface rather than how much copper was bought. This complete guide sets out the five commercial roughness grades, the skin-depth arithmetic that ranks them, and the measured cost of getting it wrong: the same standard foil that adds 8 % to an FR-4 link adds 45 % to a link on Rogers 5880.

Foil weight is the number printed on the datasheet and it answers exactly one question: how much copper is there for direct current. Half an ounce is 17.5 µm, one ounce is 35 µm, two ounces is 70 µm, and the resistance per square falls in proportion. For a power plane or a 3 A rail that is the whole story.

For a signal at 10 GHz it is almost none of the story. Alternating current crowds into the outer skin of the conductor, and the depth it occupies is set by frequency, not by foil weight: about 0.65 µm in copper at 10 GHz. A one-ounce foil is therefore 54 skin depths thick and a half-ounce foil is 27, and the current cannot tell the difference. What it can tell the difference between is a surface that is smooth and one that is a field of nodules, because the path the current has to follow over that topography is longer than the straight line, and at 10 GHz the nodules are several skin depths tall.

That inversion is the whole subject of this guide. The original version of this article listed four foil types and described their roughness correctly, but it stopped before the arithmetic: it did not say which of the two foil surfaces carries the radio-frequency current, how the penalty scales with frequency, or why foil grade matters enormously on one laminate and hardly at all on another. Those three questions decide whether a foil specification is worth anything.

Skin depth in copper is 2.06 µm at 1 GHz and falls as the square root of frequency, so δ = 2.06 / √(f in GHz) micrometres. The table below is the ruler against which every roughness number in this article should be read.

Two things follow. First, foil weight cannot be a loss lever at these frequencies, because 98 % of the copper is not carrying the signal. Second, roughness is not a fixed handicap but a frequency-dependent one: a surface that is 2.4 skin depths deep at 1 GHz is 12.8 deep at 28 GHz. This is why a foil that measures acceptably on a 2.4 GHz board turns into a problem on the same board redesigned for 28 GHz, with nothing changed except the clock.

Almost every PCB foil starts as one of two products. Electrodeposited (ED) foil is grown onto a rotating titanium drum from a copper sulphate bath; the side that grew against the drum is glossy and smooth, the side that grew outward is matte and rough. Rolled annealed (RA) foil is cast and then rolled down through mills, which leaves a layered grain structure, a much smoother surface on both sides, and a considerably higher price.

RA foil is smooth for a structural reason rather than a marketing one, which is why it is the natural choice for a 30 GHz flex or a fine-line antenna on polyimide. It is not, however, the automatic choice for a rigid board: the same layered grain that survives bending also has lower peel strength after treatment than a nodular ED surface, and RA foil above 1 oz is difficult to source. On a rigid PTFE or hydrocarbon stack, 1 oz ED foil of the right grade is normally the better engineering and commercial answer.

Between the bare drum surface and the coarsest matte tooth there are five commercial grades in common supply. The names are not standardised — IPC-4562 defines composition, weight and tensile properties, not roughness classes — so two suppliers’ “VLP” can differ by half a micrometre, and the only reliable specification is a measured Rz with the measurement method named.

The peel column is the trade being made, and it is the reason low-profile foil is not automatically better. Adhesion comes from mechanical keying plus the silane coupling layer; taking away the tooth takes away most of the keying, so HVLP and ULP rely on a chemical bond and a carefully matched prepreg. On an FR-4 multilayer that is routine. On PTFE it is where delamination starts, which is the subject of section 8.

Every foil has two faces and they are not equivalent. The treated face is bonded to the laminate; the untreated face is either the outer surface of the finished board or, on an inner layer, another bonded face. The current at high frequency flows where the electric field is strongest, which is the conductor surface facing the reference plane — that is, the bonded interface on the ground side of a microstrip.

Standard foil puts its rough matte side against the laminate. The radio-frequency current therefore runs over the coarsest surface the foil has. Reverse-treated foil is the mirror image: the fine nodules are on the side that bonds, and the rougher matte side ends up facing away, where on an outer layer it is buried under 20–25 µm of plated copper and then etched. That inversion, not the headline Rz figure, is the actual benefit of RTF, and it explains a result that surprises designers: a foil that is smooth on the air side and rough on the laminate side loses almost as badly as standard foil, because the surface the current sees never improved.

For stripline the point doubles. Both conductor surfaces face a reference plane, so both interfaces matter and the benefit of a low-profile grade is applied twice. On a symmetric stripline built from two sheets of the same foil, the loss difference between STD and HVLP is therefore larger than a microstrip comparison would suggest — worth remembering when a stack is specified as “microstrip in, stripline out” on the same laminate.

The penalty is best expressed as a loss budget at 10 GHz on a 50 Ω microstrip, because that is where the site’s existing measurements sit and where the comparison is honest. The dielectric term follows α_d ≈ 2.6 · f_GHz · √D_k · D_f dB/in, so it can be calculated for each material; the copper term is what remains of the measured total with smooth foil; and the last column adds the measured penalty of standard roughness.

The table contains the single most useful fact in foil selection: the penalty is a fixed number of tenths of a dB per inch, so its percentage depends entirely on what it is being added to. On FR-4, where the dielectric already loses 1 dB/in, no foil grade will rescue the design and paying for ULP is money thrown away. On 5880, where the dielectric loses 0.035 dB/in, the foil is the largest single term in the budget and the grade is worth arguing about. The corollary is a rule of thumb worth carrying: choose the foil after the laminate, never before it.

Attempting to compute the penalty instead of measuring it is where most articles go wrong. The standard Hammerstad correction, K = 1 + (2/π) arctan(1.4 (Δ/δ)²), is valid while the roughness amplitude is comparable to or below the skin depth, and saturates above that. At 10 GHz a 5 µm Rz surface is nearly eight skin depths deep, far outside the model’s range, so the formula predicts a similar penalty for RTF and STD that measurement refuses to confirm. Roughness belongs in a measurement, not in a closed form — and the insertion-loss measurement that captures it, together with the D_f and impedance measurements it has to be read alongside, is set out in electrical characteristics in high-frequency PCB manufacturing.

None of the above makes weight irrelevant — it makes weight a mechanical, thermal and process variable rather than an electrical one at high frequency. Four consequences scale directly with weight.

The four consequences are: current capacity, which scales with cross-section and roughly halves on an inner layer; etch capability, because undercut is proportional to thickness, so heavy foil forces wider lines and wider spaces; impedance, which shifts by a couple of ohms when the same drawn width is built on thicker foil, because the conductor’s top surface moves further from the reference plane and the fringing field changes; and thermal spreading, where heavy copper works as a heat spreader under a hot component. The finished-thickness column is the one that catches designers out: an outer layer drawn at 0.10 mm on 1 oz foil finishes as a 50–60 µm tall, 0.13 mm wide trapezoid, while the identical image on an inner layer finishes as a 35 µm tall, 0.08 mm wide one. Impedance coupons are therefore layer-specific, as covered in impedance control in high-frequency PCB manufacturing, and the width arithmetic is worked through in PCB etching.

The DC side of the same question — how much copper is enough for a given current, and how plating adds to it — is set out in the performance and role of PCB copper thickness and in copper thicknesses in high-frequency PCBs. The distinction that matters here is that those articles answer “how much copper”, and this one answers “which surface”.

Hydrocarbon and ceramic-filled thermoset laminates such as RO4003C and RO4350B bond to treated ED foil by the same mechanism as FR-4, and a standard or RTF grade can be used without drama. PTFE is different in kind. It has no polar groups to hydrogen-bond to a silane, its surface energy is among the lowest of any polymer, and it cold-flows under pressure, so adhesion has to be manufactured rather than assumed.

Three routes are used. Sodium naphthalenide treatment etches the PTFE surface to leave a carbonaceous, chemically active layer that can be bonded; it is also the only practical route for plated through holes in PTFE, because permanganate desmear does nothing to a fully fluorinated polymer. A FEP or bonding-film interlayer melts and forms a genuine weld at 290–315 °C, which is why 5880-type stacks are laminated far above FR-4 temperatures. And low-flow prepreg can be used as the bond ply, at 180–190 °C for the PTFE-compatible products.

This is the context in which HVLP foil on PTFE fails. Reducing the tooth removes the mechanical component of adhesion on a surface that already offers nothing chemical, so the specification has to be paid for with a bonding film or a treatment that the foil supplier may not offer on that grade. The failure mode is not a low peel reading at incoming inspection but a blister or a delamination after three reflows, and it is common enough that there is a dedicated article on preventing copper foil delamination on RO5880 boards. When a 5880 design needs both low loss and reliability, the practical answer is usually RTF at 1/2 oz with a proven treatment rather than ULP.

Inner layers keep the foil they were laminated with. Outer layers are pattern-plated afterwards, which adds 20–25 µm of copper to the surface and to the hole walls, so the finished conductor is 50–60 µm thick on a 1 oz base. That plating is columnar and relatively smooth compared with a matte foil surface, which means the outer layer’s air-side surface is not the foil’s surface at all — it is plated copper, then etched, then covered in solder mask.

The consequence for foil selection is that on an outer microstrip only one of the two conductor surfaces is the foil interface that matters, the one against the laminate, and the plating has already smoothed the other. On an inner stripline both surfaces are foil interfaces. A stack that mixes the two, common in RF front ends where the antenna feed is on the outer layer and the filter is buried, should therefore use the low-profile grade on the layers where it is paid for twice and can economise on the outer layer, subject to the plating and etch limits of the thinner base foil.

Solder mask and surface finish then sit on top and change the picture again. At 10 GHz the current is in the outer 0.65 µm, so an electroless nickel layer 3–6 µm thick is five to nine skin depths of a metal with 2.2 times the resistivity of copper: the finish, not the foil, becomes the dominant conductor term. That is a separate decision, covered in surface treatment processes in PCB manufacturing, but it explains why specifying HVLP foil and then finishing with thick ENIG is a contradiction.

Foil arrives at the fabricator as a roll 600 mm to 1200 mm wide and 18 µm to 70 µm thick, and most of the defects that reach the customer are created between the roll and the press. A wrinkle that survives lamination becomes a local thickening of the dielectric and a local thinning of the copper; on a 0.254 mm stack a 10 µm wrinkle is a 4 % dielectric change there, which is a couple of ohms of impedance in one spot and an etch-resist failure waiting to happen.

Three controls address it. Foil tension is set per roll width and per weight, and it is not the same setting for 17.5 µm and 70 µm. Lay-up happens in a clean, low-particle environment because a single 25 µm particle under the foil becomes a dent that no downstream process removes. And incoming foil is inspected for orange peel and for dents on the drum side, since a defect on the bonding surface cannot be recovered by plating. On large panels the handling window is short: a 600×1200 mm sheet of 17.5 µm foil will crease under its own weight if it is picked up unsupported.

Foil is a line item in the laminate price, not in the fabrication price, which is why the grade decision is often made by a purchasing department that has never seen a loss plot. The premiums are real: rolled annealed foil costs several times an electrodeposited foil of the same weight, and HVLP and ULP are supplied by a limited number of mills, so the true cost is lead time and minimum order rather than price per kilogram.

The engineering counter-argument is arithmetic. On a 5880 stack, moving from standard to HVLP removes roughly 0.07 dB/in at 10 GHz — about 20 % of the total — and more at 28 GHz, because the penalty grows as the skin depth shrinks. On an FR-4 stack the same change removes about 0.02 dB/in, which is less than the batch-to-batch variation in D_f. So the question is never “is low-profile foil worth it” but “on which laminate”, and the answer is decided by the dielectric loss number, not by the frequency printed on the drawing.

These five claims appear in most foil articles, including the earlier version of this one, and each is wrong in a way that costs money.

Five lines turn foil from a commodity into a controlled input. 1. Weight per layer, in ounces and micrometres, remembering that outer layers finish 20–25 µm thicker. 2. Grade with a measured Rz, not just the trade name, and with the measurement method named. 3. The bonding-surface requirement, stated as the surface against the laminate, since that is the one carrying the current. 4. Peel strength to IPC-TM-650 2.4.8, with the acceptance value that the laminate system can actually hold. 5. Treatment compatibility with the resin system — silane type for epoxy and hydrocarbon, sodium naphthalenide or FEP film for PTFE.

With those five on the drawing, a foil dispute becomes a measurement. Without them, it becomes a conversation about whose “low profile” was meant.

Copper foil is described by weight and specified by roughness, and the two answer different questions. Weight sets direct-current resistance, current capacity, etch capability and thermal spreading. Roughness sets what happens to the signal at 10 GHz and above, where the current occupies less than two per cent of the metal and follows the topography of the surface facing the reference plane. The five commercial grades span Rz from about 8 µm down to 1.5 µm, and the same grade that costs 8 % of the loss on FR-4 costs 45 % on 5880.

Three decisions follow and they are sequential. Choose the laminate on dielectric loss, then choose the foil grade on the share that copper represents in the budget, then confirm that the grade bonds to that resin system without a delamination risk. Doing them in the other order — specifying ULP foil on a PTFE stack because the frequency is high — is how boards pass electrical test and fail reliability.

XCE PCB laminates and etches all five grades on conventional and high-frequency builds: 2 to 72 layers, panels to 600×1200 mm, impedance held to ±10 %, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. Foil grade, laminate and finish are quoted as one system rather than three line items, because the three interact — the plating side of that interaction is set out in plating in high-frequency PCB manufacturing and the press side in lamination for high-frequency PCBs.