I. Core Principles of High-Frequency PCB Impedance Design

In high-frequency signal transmission, impedance matching is critical for minimizing signal reflection and ensuring signal integrity. Impedance deviation must be controlled within ±5% (±3% for millimeter-wave applications); otherwise, return loss (S11) will occur, affecting signal quality. Impedance design requires comprehensive calculations that take into account transmission line types, substrate characteristics, and process parameters.

II. Common Impedance Types and Design Requirements for High-Frequency PCBs

RF Signals (1–28 GHz)

Impedance Type: Single-ended 50 Ω (e.g., antenna feedlines, power amplifier outputs).

Accuracy Requirement: ±3%, return loss ≤ –15 dB (at 10 GHz).

Design Considerations: Use microstrip line structures, control trace width and dielectric thickness, and avoid signal reflections that cause power attenuation.

High-Speed Digital Signals (5–56 Gbps)

Impedance Type: Differential impedance (e.g., 85 Ω for PCIe 6.0, 100 Ω for USB4).

Accuracy Requirements: ±5%; both insertion loss (≤1 dB/100 mm at 25 GHz) and crosstalk (near-end crosstalk ≤–25 dB) must be controlled.

Design Key Points: Use a stripline structure to ensure that the spacing and width of the differential pairs match, thereby avoiding timing inconsistencies.

Millimeter-Wave Signals (28–100 GHz)

Impedance Type: 75 Ω or 100 Ω single-ended impedance.

Accuracy Requirements: ±2%; control the surface roughness of the trace edges (Ra ≤ 0.3 μm) to reduce surface loss.

Design Considerations: Use low-loss materials (e.g., Rogers RO3000) and optimize trace width and dielectric thickness to prevent signal distortion.

III. Core Principles of High-Frequency PCB Stackup Design

Signal Integrity (SI)

Impedance Control: Adjust trace width, dielectric thickness, and dielectric constant to match the transmission line’s characteristic impedance with the source and load impedances.

Return Path: High-frequency signals form return currents on the reference plane via electromagnetic coupling; ensure a continuous reference plane to prevent segmentation.

Crosstalk Management: Control electromagnetic coupling between adjacent signal lines by adjusting trace spacing, interlayer dielectric thickness, and reference plane continuity.

Power Integrity (PI)

Decoupling Capacitor Placement: Strategically place decoupling capacitors based on the power plane’s resonance frequency to create a low-impedance power delivery network.

Planar Capacitance Effect: Utilize the planar capacitance formed by the power plane and ground plane to supply high-frequency energy; control the interlayer dielectric thickness and dielectric constant.

Resonance Suppression: Suppress power plane resonance by reducing the power plane area and increasing the number of decoupling capacitors.

Structural Symmetry

Symmetrical Dielectric Thickness: Distribute dielectric thickness symmetrically across all layers to prevent board warping.

Impedance Symmetry: Keep impedance variations between similar signal lines (such as differential pairs within the same group) within ±10%.

Via Symmetry: Critical signal vias are distributed symmetrically to reduce signal reflections caused by sudden changes in via impedance.

Reference Plane Selection

Prioritize Ground Layers: Due to their lower impedance and superior noise suppression capabilities.

Reference Plane Switching: When switching reference planes is necessary, add return vias near the signal lines.

Signal Direction on Adjacent Layers: Signal routing on adjacent layers should be perpendicular to minimize crosstalk caused by parallel routing.

IV. Common Layer Stack-Up Schemes for High-Frequency PCBs

4-Layer Boards

Scheme 1: TOP-GND-PWR-BOTTOM

Applicable Scenarios: Cost-sensitive designs with low EMI requirements.

Features: Complete GND layer, flexible PWR layer segmentation, and lower cost.

Scheme 2: TOP-PWR-GND-BOTTOM

Applicable Scenarios: High-speed signal designs requiring a complete reference plane.

Features: Good signal quality on the TOP and BOTTOM layers, but power layer segmentation requires caution.

6-Layer Boards

Scheme 1: TOP-GND-S2-PWR-GND-BOTTOM

Applicable Scenarios: High-speed digital circuit design.

Features: Dual-layer continuous reference plane; good signal quality on the S2 layer.

Scheme 2: TOP-S2-GND-PWR-GND-S3-BOTTOM

Applications: Designs requiring a large number of signal layers.

Features: Provides more routing layers, but attention must be paid to the distance between signal layers and reference planes.

8-Layer Board

Recommended Configuration: TOP-GND-Signal-PWR-GND-Signal-GND-BOTTOM

Applications: High-frequency, high-speed, and high-density designs.

Features:

All signal layers are adjacent to ground reference planes, supporting mixed routing of microstrip and stripline.

Strongly coupled power and ground pairs suppress PDN impedance resonance.

Magnetic flux cancellation between dual ground layers significantly reduces common-mode radiation.

V. Key Processes for High-Frequency PCB Impedance Control

CAM Design and Parameter Compensation

Pre-compensation for trace width/spacing: Account for etching deviations by pre-compensating trace widths during CAM design (e.g., for a 0.2mm trace width, pre-compensate by +0.02mm).

Dielectric Thickness Control: Adjust the dielectric thickness parameters in CAM based on substrate thickness deviations to ensure impedance stability.

Ground Plane Design: Avoid windows or notches in the ground plane to ensure the signal loop area is minimized.

Etching Process Precision Control

Etching Solution Parameter Optimization: Use an acidic etching solution and control temperature and concentration to reduce line width deviations.

Etching Uniformity Control: Use spray-type etching equipment to ensure uniform distribution of the etching solution across the PCB surface.

Line Width Inspection and Feedback: Immediately after etching, perform a full inspection of line widths using a laser profilometer to ensure compliance with design requirements.

Lamination Process Dielectric Thickness Control

Substrate Cutting Accuracy: Keep substrate cutting dimensional deviations ≤±0.05 mm prior to lamination to avoid localized dielectric thickness variations.

Precise Control of Laminating Parameters: Control laminating temperature, pressure, and dwell time to ensure stable dielectric thickness.

Post-Laminating Thickness Inspection: Measure dielectric thickness using an ultrasonic thickness gauge to ensure compliance with design requirements.

VI. High-Frequency PCB Impedance Testing and Calibration

In-Line Impedance Testing

Impedance Tester Selection: Use a high-frequency impedance analyzer (frequency range 1 MHz–40 GHz) that supports single-ended and differential impedance testing.

Test Sample Preparation: Prior to each production batch, prepare impedance test coupons containing impedance circuits with varying trace widths and spacing.

Online Testing Process: Conduct sampling impedance tests after lamination and etching. If deviations exceed ±5%, halt production to analyze the cause and adjust the process.

Batch Production Impedance Calibration

Periodic Process Validation: For every 100 high-frequency PCBs produced, select one for full-frequency impedance testing and record impedance deviation trends.

Equipment Calibration: The impedance tester is calibrated monthly, while the etching machine and laminating machine are calibrated quarterly.

Root Cause Analysis and Improvement: If the impedance pass rate for a batch falls below 95%, the CAM parameters, etching parameters, and laminating parameters for that batch must be traced, and corrective actions must be implemented.