The RF PCB production process is not a different process from the production of a high-frequency PCB. It is the same nine steps with five additions, and the additions are where RF boards lose their performance in a factory that is otherwise competent. A connector that is soldered with the wrong number of ground pins, a lid screwed at 8 mm pitch over a 30 mm cavity, a V-cut 0.5 mm from an antenna element, a coupon measured without de-embedding, and a plated through hole in PTFE that was desmeared with permanganate — each of these leaves a board that passes continuity, passes AOI and fails in the chamber.
The Five Additions, in the Order They Bite
A high-frequency board and an RF board go through the same fabrication sequence: cut, image, etch, laminate, drill, plate, mask, finish, test. What separates them is that an RF board also carries a defined launch, a defined enclosure, a defined panel context and a defined measurement plane, and each of those four creates a production requirement that the sequence above does not contain. The fifth addition is material-driven: on a PTFE laminate, hole metallisation stops being a routine step.
| Addition | What it is | Why it does not appear on an HF board | What it fails as |
|---|---|---|---|
| Connector launch | SMA, 2.92 mm or waveguide flange soldered to an edge pad with ground pins | An HF board is usually measured at a coupon, not driven at a connector | Return loss degrades above 6 GHz while the line itself measures correctly |
| Shielding cavity | A metal lid 3–8 mm above the RF layer, screwed or soldered | Digital boards use cans over individual components, not cavities over traces | A resonance inside the band, appearing as gain ripple rather than as loss |
| Panelisation | V-cut, tabs, board edge distance, array orientation | On a high-frequency board the edge is mechanical; on an antenna it is electrical | Edge elements shift in frequency and the array sidelobes rise |
| De-embedded measurement | Coupon plus fixture plus calibration, with the fixture removed mathematically | Impedance alone can be certified from a TDR coupon | Loss reported 0.1–0.3 dB per inch wrong, in either direction |
| PTFE hole metallisation | Sodium naphthalenide or plasma instead of permanganate desmear | Epoxy boards desmear with permanganate, which does nothing to PTFE | Voided or non-adherent plating that passes visual and fails thermal cycling |
Each of the five can be specified, measured and accepted. None of them is covered by the generic process instructions a fabricator issues for a high-frequency build, and that gap is the subject of this article. The nine-step arithmetic of how each fabrication step spends the impedance budget is treated separately in processing considerations for high-frequency PCBs; this article assumes that budget and asks what else an RF board needs.
What the Earlier Version Left Out, and Three Things It Got Wrong
The earlier version of this page described material selection, layout, impedance matching, etching, drilling, surface treatment and testing. All seven topics are real, none of them carried a number, and three of the statements reverse the engineering. The corrections matter because they are the same three phrases that appear in most RF fabrication notes.
| Statement in the original | What is actually true |
|---|---|
| Immersion gold (ENIG) is suitable for high-frequency applications because it has good solderability | ENIG puts 3–6 µm of nickel in the current path, and the 0.05–0.10 µm gold above it is eight to fifteen times thinner than the gold skin depth at 10 GHz. Nickel has 2.04 times the sheet resistance of copper: 0.10–0.15 dB/in at 10 GHz and 0.20–0.30 dB/in at 28 GHz. ENIG is chosen for assembly, not for loss |
| HASL is suitable for standard applications but does not perform as well as immersion gold for high-frequency signals | The ranking is right and the reason is wrong. HASL at 250–260 °C is a thermal shock to a PTFE laminate with 200–240 ppm/K of Z expansion, and the air knife can press the dielectric thinner and change the impedance. Its thickness also varies from 1 to 25 µm, which is a coplanarity problem for fine pitch. Neither issue is about high frequency as such |
| The concentration and temperature of the etching solution must be strictly controlled to prevent line damage | True but unusable. The quantity that is actually controlled is the side etch, which equals copper thickness divided by the etch factor: 23 µm per side on 1 oz copper at an etch factor of 1.5, 47 µm on 2 oz. That is 7 % of a 0.30 mm line and 3 % of a 0.8 mm line, and it is the etch that decides whether the finished width matches the one the impedance was calculated for |
| Drilling quality ensures the hole diameter and position to avoid short circuits and open circuits | Diameter and position do not produce shorts or opens on a drilled through hole; the plating does. What diameter and position set is the annular ring, the aspect ratio and the effective reference-plane clearance — which is an impedance and a stub problem, not a continuity problem |
| The seven topics listed above constitute the production considerations | They constitute the generic process. The five additions in the previous section — launch, cavity, panel, de-embedding, PTFE plating — are absent, and they are the five that a factory cannot infer from a Gerber |
One structural point follows from the last row. A fabrication note written for a high-frequency board tells the factory how to make a controlled-impedance laminate. A note written for an RF board has to tell it how the board will be connected, enclosed, panelised and measured, because those four decisions are made before the first drill and cannot be recovered afterwards.
On an RF Board the Acceptance Criteria Are in dB, Not in Continuity
The reason the five additions matter is that they move quantities which the standard acceptance chain does not observe. Continuity proves copper where copper was drawn. AOI proves the pattern matches the artwork. Impedance proves the line is 50 Ω. None of the three proves that the board will deliver the gain the link budget assumed, and the five additions sit precisely in the gap.
| Acceptance axis | What it proves | What it cannot see | How an RF board is judged |
|---|---|---|---|
| Continuity and AOI | The pattern is the artwork | Loss, launch, resonance, stub | Prerequisite only |
| Impedance, TDR on a coupon | The line is 50 Ω ±10 % | Dielectric loss, copper roughness, finish, cavity | One of three axes |
| Insertion loss, VNA on a coupon | dB per inch at the band of interest | Launch and enclosure behaviour, because the coupon has neither | Second axis; needs de-embedding to be comparable |
| Return loss with the connector and lid fitted | The assembly behaves as a system | Nothing — this is the only end-to-end number | Third axis; requires a first-article assembly, not a bare board |
Boards that fail in the chamber almost always pass the first two axes and were never measured on the third. That is why the five additions have to be treated as production items rather than as application notes: they are the only ones whose failure mode is invisible to the acceptance chain a high-frequency board uses.
Consideration One: The Connector Interface Is a Transmission Line
An SMA launch is not a solder joint with a signal pin. It is a transition from a coaxial cross-section to a planar one, and the transition has an inductance set by the ground return path. A single 1 mm ground pin is about 1 nH, which is 63 Ω of reactance at 10 GHz; four pins placed within 1.5 mm of the centre pin come to about 16 Ω. The difference between two pins and four is the difference between a launch that works to 6 GHz and one that works to 18 GHz, and it is decided in the footprint, not in the soldering.
| Interface | Usable band | Ground return requirement | Production failure mode |
|---|---|---|---|
| SMA, standard | DC–18 GHz | 4 pins within 1.5 mm, plus a ground via beside each | Pin starvation, or a thermal relief in the ground pad that adds inductance |
| SMA, precision | DC–26.5 GHz | Same, with the launch kept under 1 mm long | Excess solder fillet on the centre pin, which changes the launch capacitance |
| 3.5 mm / 2.92 mm | 33 / 40 GHz | 4–6 pins, ground vias at ≤ 0.5 mm pitch | Pad geometry copied from an SMA footprint |
| 2.4 mm / 1.85 mm | 50 / 67 GHz | Full ground collar, vias on a 0.4 mm grid | Laminate under the launch too thick for the pin diameter |
| Waveguide flange | Band-dependent (WR-28: 26.5–40 GHz) | Screw pattern and flange flatness | Flange bow across the split, leaking 1–2 dB |
Three production rules follow. The launch pad is drawn to the connector drawing, not approximated. The ground vias under the launch are placed before the panel is laid out and are not moved by the copper pour. And the connector is attached after the impedance coupon has been measured, so that a launch problem is not mistaken for a laminate problem. The transmission-line geometry itself is covered in microstrip and stripline design.
Consideration Two: The Cavity Is a Resonator
A lid over an RF trace forms a rectangular cavity, and a rectangular cavity resonates. For a 30 × 20 mm lid at 3 mm height the lowest mode is near 9 GHz, which lands inside a great many bands. The symptom is not a loss of signal but a ripple: gain that peaks and dips across a few hundred megahertz, which is usually blamed on the amplifier and is a mechanical part.
The number to compute is f = (c/2) · √((m/a)² + (n/b)²) for the cavity walls a and b, and the design response is to keep the lowest mode above the band by lowering the lid, adding a screw or a septum inside the cavity, or placing absorber. Screw pitch matters as much as screw presence: at 10 GHz the free-space wavelength is 30 mm, so a 3 mm pitch is λ/10 and a 15 mm pitch is λ/2, which is a slot radiator rather than a seam.
| Cavity, a × b × h | Lowest mode | What it does to a 5–6 GHz board | Production control |
|---|---|---|---|
| 20 × 15 × 5 mm | about 12.5 GHz | Harmless in band; watch the second mode | Lid flatness 0.1 mm, screw pitch 5 mm |
| 30 × 20 × 3 mm | about 9 GHz | Outside a 5–6 GHz band, but a 2–3 dB ripple if the band reaches 8 GHz | Septum or absorber, screw pitch 3 mm |
| 40 × 30 × 5 mm | about 6.3 GHz | Inside the band: gain ripple across the whole channel | Split the cavity, or lower the lid to 2 mm |
The production consequences are unglamorous and often skipped: the lid has to be flat to 0.1 mm over its length, the screw pattern has to be in the fabrication data rather than chosen on the bench, and the ground stitching vias along the cavity wall have to be at a pitch that keeps the wall a wall. A cavity is only a shield if its perimeter is continuous at the frequency in use.
Consideration Three: Panelisation Is an Electrical Decision
On a digital board, panelisation is a material-utilisation calculation. On an RF board carrying antenna elements or coupled lines near the edge, it is part of the circuit. Three mechanisms are involved. Current on an edge element sees a different environment when a neighbouring board is 2 mm away than when it is in free space, which shifts its resonant frequency. The V-cut leaves a residual web of 0.3–0.5 mm that behaves as a dielectric-loaded slot at 20 GHz and above. And depanelling stress acts on a laminate that cold-flows: PTFE compressed by 4 % changes a 50 Ω line to 48.8 Ω and does not recover.
| Panel decision | Electrical consequence | Working rule |
|---|---|---|
| RF line to board edge | Edge current sees the panel gap, not free space | ≥ 3h from the edge, and never less than 1 mm; antenna elements need ≥ λ/4 |
| V-cut versus routing | Residual web acts as a slot above 20 GHz | Route with 1.6–2.0 mm slots for any board above 20 GHz; V-cut only below 6 GHz |
| Tab position | Stress concentrates at the tab and cold-flows PTFE | Tabs on mechanical edges, never across an RF line; 5 mm minimum tab width |
| Array orientation | Grain direction changes expansion and prepreg shrink | All boards in a panel with the same grain direction, recorded on the traveller |
| Separation method | Router burr and dust on PTFE | No laser (PTFE decomposes above 400 °C, releasing HF), no water jet; routed and deburred |
The rule that covers most of it is that the panel is designed with the RF engineer present, not after the Gerbers are released. A 0.5 mm change in edge distance is a 1–2 % frequency shift on a patch element, which is inside the tuning range of nothing.
Consideration Four: You Cannot Measure It Without a Fixture
An insertion-loss figure is meaningless without a defined measurement plane. The coupon is 50 mm of line with two launches; the launches and the fixture contribute their own loss and their own reflections, and at 10 GHz a pair of mediocre SMA launches can add 0.2 dB, which on a 50 mm line is 0.10 dB per inch — comparable to the dielectric term of the material being tested. Either the fixture is de-embedded or the number is not a material property.
Two methods are used in production. The 2x-thru method measures a through line of exactly twice the coupon length and uses it to remove the fixture, which is fast and adequate to about 30 GHz. TRL calibration with on-board standards removes the fixture as part of the calibration and is better above that, at the cost of on-board real estate. In both cases the coupon has to be built on the same stack, the same foil and the same finish as the product, and it has to be measured before the surface finish ages — an OSP coupon measured three months late reads differently from one measured in the week it was built.
| Measurement requirement | Minimum | Why it matters in production |
|---|---|---|
| Coupon stack | Same cores, same bondply, same foil, same finish, same panel | A coupon from a different panel proves the process, not the board |
| Line length | ≥ 50 mm, long enough for the fixture term to be a small fraction | At 20 mm the launch error is 25 % of the result |
| Calibration | 2x-thru to 30 GHz, TRL above | Without it, two labs disagree by 0.1 dB/in on the same board |
| Repeatability | 0.05 dB/in on a repeated measurement | A result inside the lab scatter cannot be used to reject a lot |
| Return loss of the fixture | ≤ −15 dB across the band | Ripple from a bad launch is read as line loss |
The acceptance logic that uses these numbers, and the test ladder that precedes them, are set out in testing in high-frequency PCB production. What belongs here is the production rule: the coupon and the fixture are part of the order, quoted with the boards, and the de-embedding method is named in the purchase order so that the delivered number and the simulated number are the same kind of number.
Consideration Five: PTFE Metallisation Is Not a Generic Step
The desmear that makes an epoxy board reliable does nothing to PTFE. Permanganate attacks the epoxy in the drill smear; PTFE is resistant to it, so the smear stays, and the palladium catalyst deposits on a surface that is chemically inert. The result is a plating layer that adheres at the rims, looks continuous in cross-section at low magnification, and fails a thermal cycle when the Z expansion of the laminate (217–237 ppm/K against 17 for copper) pulls the barrel away from the wall.
Two treatments work. Sodium naphthalenide etches the PTFE surface chemically and leaves a carbonaceous layer that the catalyst can bond to; it is effective, aggressive, and has to be controlled by immersion time because over-treatment produces a weak boundary layer. Plasma treatment is more uniform across a panel and better on small holes; it is slower and needs the right gas chemistry. Either way the process window is a qualification item, not a line setting, and the acceptance evidence is a thermal-cycle test on a daisy chain rather than a cross-section.
| Item | Requirement on a PTFE build | Why the epoxy default fails |
|---|---|---|
| Desmear | Sodium naphthalenide or plasma; permanganate alone is not sufficient | Permanganate does not attack PTFE, so smear remains under the plating |
| Aspect ratio | ≤ 6:1 for PTFE against 10:1 on FR-4 | Solution exchange in a 0.3 mm hole through 1.6 mm is marginal for a high-surface-tension etchant |
| Plating ductility | ≥ 20 % elongation | 1.6 mm of 5880 expands about 82 µm across a 215 K reflow excursion, against 6 µm for the barrel |
| Barrel copper | ≥ 25 µm, and ≥ 30 µm on high layer counts | Thin, brittle plating cracks at the knee where the strain concentrates |
| Back-drill or blind via where a through via is longer than λ/4 of the band | A 1.6 mm stub resonates near 33 GHz on PTFE, 23 GHz on FR-4 | |
| Bake | Not required for PTFE; required for FR-4 cores at 120–150 °C | Baking PTFE achieves nothing and risks dimensional change on thin cores |
The drilling and plating windows themselves are covered in drilling in high-frequency PCB manufacturing and plating in high-frequency PCB manufacturing. The production point is that a PTFE order has to carry the treatment route explicitly, because a fabricator that runs mostly FR-4 will apply the default and see no reason to mention it.
The Control Plan for an RF Build
Ten items cover the five additions plus the four process controls that RF boards are most sensitive to. Each has a window, a measurement and a named owner, which is the difference between a control plan and a list of good intentions.
| Control item | Window | Measured by | Failure it prevents |
|---|---|---|---|
| Laminate batch and Dk | Dk within the datasheet tolerance, batch recorded | Supplier certificate plus incoming SPDR check | Silent 2 % impedance shift between lots |
| Dielectric height after press | ±10 % of the design h | Cross-section from the panel edge | ±6 % impedance — the largest single term |
| Finished line width | ±25 µm, with side-etch compensation | AOI plus cross-section | 2.8 % impedance at 0.254 mm h, 5.5 % at 0.127 mm |
| Foil roughness | Per the specified class (HVLP ≤ 2 µm Rz) | Incoming certificate, or a lot coupon at 10 GHz | 0.06–0.10 dB/in of unexplained conductor loss |
| Solder mask thickness | 15–30 µm over the trace, per drawing | Cross-section | 1–3 Ω of impedance and 0.02 dB/in at 10 GHz |
| Surface finish | Ni 3–6 µm, Au 0.05–0.10 µm (ENIG) | XRF plus cross-section | 0.10–0.15 dB/in at 10 GHz if nickel runs thick |
| Launch footprint | Ground vias per the connector drawing | First-article return loss to the band edge | A launch that fails above 6 GHz |
| Cavity lid flatness | 0.1 mm over the length, screw pitch ≤ λ/10 | CMM plus first-article sweep | Gain ripple inside the band |
| Panel edge distance | ≥ 3h and ≥ 1 mm; ≥ λ/4 for antennas | Panel drawing review before release | 1–2 % frequency shift on edge elements |
| Coupon and de-embedding | Same stack, same panel, 2x-thru or TRL named | VNA, repeatability 0.05 dB/in | A loss number that cannot be compared with the simulation |
Where the Yield Actually Goes
Scrap on RF builds is not distributed like scrap on digital builds. The five additions account for a disproportionate share because each of them fails in a way that inspection does not catch, and because each is decided early and paid for late. The table below is the order in which the causes appear in practice, with the point at which they become visible.
| Failure | Where it is created | Where it is found | Cost of finding it late |
|---|---|---|---|
| Launch return loss out of spec | Footprint design | First-article VNA, after assembly | Rework or scrap of an assembled board |
| Cavity resonance in band | Mechanical design | Chamber test | New lid tooling |
| Edge element frequency shift | Panelisation | Antenna range | New panel, new stencil |
| Voided PTFE plating | Desmear route | Thermal cycling, months later | Field return |
| Impedance out at the part, in at the coupon | Bondply flow variation across the panel | Customer TDR on the product line | Whole lot |
| Loss above the simulated value | Foil or finish substitution | Nobody, unless a coupon is measured | Margin quietly consumed |
Only the last row is routinely invisible, and it is the one that a de-embedded coupon measurement converts into a number. That is the case for treating the five additions as production items: four of them have a visible failure and one does not, and the invisible one is the one that decides whether the next design has margin left.
What to Write in the Fabrication Note
The five additions become controllable only when they are written down, because each of them is a decision a fabricator would otherwise make by default. Six items are enough.
One: the connector part number, its footprint drawing, and the ground-via pattern under the launch. Two: whether a lid will be fitted, its height, its screw pattern and the flatness requirement — even if the lid is a customer part, because it constrains the ground stitching. Three: the panel, with edge distance, tab positions, and the separation method, explicitly excluding laser and water jet on PTFE. Four: the coupon — same stack, same panel, length, calibration method, de-embedding method, and the acceptance window in dB per inch. Five: the PTFE treatment route, by name, with the thermal-cycle acceptance test that proves it. Six: the finish with layer thicknesses rather than the finish name, and whether any RF line is to be opened.
Those six turn a purchase order into a specification. The material side of the same stack — bondply, foil roughness, mask and finish as loss terms — is set out in RF PCB materials, and the definition of what makes a board RF in the first place is in what is an RF PCB.
Conclusion
The RF PCB production process is the high-frequency process plus five items: the launch, the cavity, the panel, the de-embedding and the PTFE metallisation. Each has a number attached. One millimetre of ground pin is 1 nH and 63 Ω at 10 GHz. A 30 × 20 mm lid resonates near 9 GHz, and a screw at λ/2 pitch is a slot rather than a seam. A V-cut residual web is a slot above 20 GHz, and PTFE compressed 4 % moves 50 Ω to 48.8 Ω permanently. A fixture that is not de-embedded contaminates the loss figure by an amount comparable to the dielectric term. And permanganate desmear does nothing to PTFE, which is why PTFE boards fail thermal cycling with plating that looked perfect.
None of the five is exotic. All five are decided before the first drill, none is visible to continuity, AOI or a TDR coupon on a bare laminate, and all five are the reason an RF board can pass every inspection it is given and still miss its link budget.
XCE PCB builds RF and mixed stacks from 2 to 72 layers, up to 600 × 1200 mm, with impedance held to ±10 %, coupon and VNA measurement quoted with the order, and samples in as fast as 24 hours. The five items above are specified per order rather than inherited from an FR-4 default.
Frequently Asked Questions
Why does an RF board fail return loss when the impedance coupon passes?
How do I stop a shielding lid from resonating?
Is immersion gold suitable for RF boards?
Why can a PTFE board pass cross-section and fail thermal cycling?
What does de-embedding change in a loss measurement?
How far should an RF line stay from the board edge?
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