The design of high-frequency PCB stack-up schemes must balance signal integrity, power integrity, electromagnetic compatibility, and cost control. Core principles include adjacent reference planes, paired power and ground planes, uniform interlayer dielectric thickness, and avoiding direct adjacency between signal layers. The following outlines specific solutions and design considerations:
I. Core Principles of High-Frequency PCB Stack-Up Design
Adjacent Reference Planes
Each signal layer must be adjacent to a continuous reference plane (ground or power layer) to shorten the signal return path and reduce crosstalk and electromagnetic radiation. High-frequency signals should preferably be routed on the top layer (e.g., Top layer), with the ground layer directly below it, forming a “signal-ground” coupling structure.
Example: In a 4-layer board, the Top layer serves as the high-frequency signal layer, and the GND layer acts as the continuous reference plane; the recommended spacing between them is ≤0.2 mm.
Power and Ground Layer Pairing
Power layers and ground layers must be placed adjacent to each other to form a low-impedance decoupling capacitor that suppresses power supply ripple. The interlayer dielectric thickness is recommended to be ≤0.3 mm to enhance the coupling effect.
Example: In a 6-layer board, the PWR layer is paired with the GND layer, with an intermediate dielectric thickness of 0.2 mm, providing a stable power distribution network (PDN).
Uniform Interlayer Dielectric Thickness
Dielectric thickness deviations must be controlled within ±0.02 mm to avoid impedance fluctuations caused by uneven thickness. The dielectric thickness between high-frequency signal layers and the reference plane must be precisely controlled.
Example: In an 8-layer board, the dielectric thickness between each signal layer and the reference plane must be consistent to prevent impedance mismatch.
Avoid Directly Adjacent Signal Layers
Adjacent signal layers are prone to crosstalk and must be isolated by ground or power layers. High-frequency signal layers should be sandwiched between reference planes to form a “shielded cavity.”
Example: In a 6-layer board, the Top layer (signal) → GND layer → Signal layer (auxiliary signal) → PWR layer → GND layer → Bottom layer (signal), with signal layers isolated by GND layers.
II. Recommended High-Frequency PCB Stack-Up Schemes
1. 4-Layer Board Solution (Suitable for WiFi 6, 5G CPE, and similar devices)
Layer Stackup:
Top (Signal Layer) → GND (Full Ground Layer) → PWR (Power Layer) → Bottom (Signal Layer)
Design Considerations:
Top Layer: Route high-frequency signals (e.g., RF differential pairs, clock signals); trace width should be designed according to impedance requirements (typically 0.2–0.5 mm).
GND Layer: Closely adjacent to the Top layer (layer spacing 0.1–0.2 mm) to form “signal-ground” coupling and reduce EMI radiation.
PWR Layer: Provides stable power to high-frequency chips; adjacent to the GND layer (layer spacing 0.2–0.3 mm) to prevent power supply noise from interfering with signals.
Bottom Layer: Routes low-speed control signals (e.g., I2C, SPI) to avoid crossing with high-frequency signals on the Top layer.
2. 6-Layer Board Design (Suitable for 5G Base Stations, Millimeter-Wave Radar)
Layer Stackup:
Top (Signal Layer) → GND (Full Ground Layer) → Signal (Auxiliary Signal Layer) → PWR (Power Layer) → GND (Isolation Ground Layer) → Bottom (Signal Layer)
Design Considerations:
Top Layer: Route high-frequency signals (e.g., millimeter-wave signal transmission); trace width should be designed according to impedance requirements.
GND Layer: Adjacent to the Top Layer to provide a stable return path.
Signal Layer: Route auxiliary signals (e.g., low-speed digital signals); avoid crossing with high-frequency signals on the Top Layer.
PWR Layer: Paired with the GND layer to form a low-impedance decoupling capacitor.
GND Layer (Isolation Layer): Isolates the Signal layer from the PWR layer to reduce crosstalk.
Bottom Layer: Routes low-speed signals or accommodates additional components.
3. 8-Layer Board Solution (Suitable for High-Performance Servers, 5G Base Stations)
Layer Stackup:
Top (Signal Layer) → GND (Solid Ground Layer) → Signal1 (Stripline Layer) → PWR (Power Layer) → GND (Solid Ground Layer) → Signal2 (Stripline Layer) → PWR (Power Layer) → Bottom (Signal Layer)
Design Considerations:
Top Layer: Route high-frequency signals (e.g., PCIe, HDMI signals); trace widths should be designed according to impedance requirements.
GND Layer: Closely adjacent to the Top layer, providing a stable return path.
Signal1/Signal2 Layers: Feature stripline structures, offering strong interference immunity and suitability for high-speed digital signal transmission.
PWR Layer: Paired with the GND layer to form multiple ground-to-power plane combinations, ensuring stable power distribution.
Bottom Layer: Used for low-speed signals or additional components.
III. Key Process Controls for High-Frequency PCB Stackup Design
Material Selection
Prioritize low-loss laminates with stable dielectric constants (e.g., Rogers RO4350B, Taconic, Isola, etc.). Standard FR4 exhibits high loss at frequencies above 1 GHz.
The dielectric constant (Dk) must be selected based on frequency response curves to ensure the accuracy of impedance calculations.
Impedance Control
Use professional tools (such as Polar SI9000 or Ansys HFSS) to precisely calculate trace width, spacing, and dielectric thickness to meet target impedance (e.g., 50Ω single-ended, 100Ω differential).
Consider the impact of the solder mask: The solder mask covers the transmission lines, increasing the equivalent dielectric constant; therefore, a margin must be factored into calculations (e.g., for a 50Ω design, the actual trace width should be reduced by 0.02mm) .
Lamination Process
During lamination, control temperature, pressure, and dwell time to ensure uniformity of dielectric thickness (tolerance ≤ ±0.01 mm).
Avoid impedance fluctuations caused by interlayer dielectric thickness variations.
Via Design
Prioritize blind or buried via technology to reduce impedance discontinuities during interlayer transmission.
Vias should be as small as possible (e.g., 0.15 mm), and ground vias should be added adjacent to signal vias to form a “signal via-ground via” shielding structure.
IV. Verification of High-Frequency PCB Stackup Design
Simulation Verification
Use software (e.g., Ansys SIwave) to simulate impedance variations along transmission lines and optimize the design (e.g., reduce via parasitic parameters, avoid abrupt impedance changes).
Impedance Testing
After lamination and etching, test 5% of the samples for impedance. If the deviation exceeds ±5%, halt production to analyze the cause and adjust the process.
Use a Time Domain Reflectometer (TDR) to measure the actual impedance of the traces on the test strips to verify compliance with design tolerances.
EMC Testing
Verify that EMI radiation complies with standards (e.g., CISPR 32) and optimize the shielding design (e.g., by adding ground via fences or using metal shielding enclosures).