How Can Power Supply Noise Interference on High-Frequency PCBs Be Resolved? Start With Target Impedance

The question of how can power supply noise interference on high-frequency PCBs be resolved is usually answered with a list of remedies — more capacitors, filters, ferrite beads, separation. The list is not wrong so much as unordered: each remedy addresses one frequency band, and applied outside its band it either does nothing or creates a resonance. This article starts from the one number that orders everything else, the target impedance of the power delivery network, then works up the frequency axis to show which component is responsible at each decade and where the energy is actually converted into noise.

Power supply noise is not a substance that leaks into a board; it is a voltage deviation produced when a current step meets an impedance. The deviation is ΔV = ΔI × Z, so the entire problem can be written as a single requirement: over the frequency range where the load draws transient current, the impedance of the power delivery network must stay below a value that keeps ΔV inside the allowed ripple.

That value is the target impedance, Z_target = V_rail × ripple % / ΔI. It is the only number in the design that can be checked, and it immediately shows why some boards are hard and some are not.

Two consequences follow immediately. A rail with a large transient and a low voltage is a hard problem, and a rail with a small transient or a high voltage is not — so “the board has power noise” is meaningless until the rail and the step are named. And the target is a broadband requirement: the impedance must stay under it from the regulator’s control bandwidth up to the frequency where the die’s own capacitance takes over, which is typically a few hundred megahertz.

The power delivery network is a chain of components, each with a frequency range where its impedance is the lowest of the chain. Noise is suppressed by whichever element is lowest at that frequency; if there is a frequency where nothing is low, that is where the noise appears.

This band structure explains why adding capacitors sometimes appears to do nothing: below 1 MHz the regulator and the bulk capacitors are already lower, and above 50 MHz the mounting inductance limits what a ceramic can do regardless of its value. The useful intervention is always in the band where the impedance is currently highest. The loop that defines the high-frequency end is the same one described in the concepts of electricity in a PCB, where return current and loop area are treated as the primary quantities.

Every real capacitor is a series RLC. Below its self-resonant frequency it behaves as a capacitor; above it, as an inductor. The resonance is set by the capacitance and the total loop inductance, which for a board-mounted part is dominated by the mounting, not by the component.

The table assumes 0.9 nH of total inductance, which is roughly what a 0402 with two short via connections achieves. The same capacitor connected through 5 mm of trace and two long vias sees 3–5 nH, and its resonance drops by a factor of two to three: the 0.1 µF part now resonates at 7 MHz and is inductive over most of the band it was chosen for. Mounting inductance, not capacitance, is the design variable — about 1 nH per millimetre of trace, 0.3–0.5 nH per via.

This is why the useful rule is not “one 0.1 µF per power pin” but “a spread of values, each placed with the shortest possible connection, with the highest-frequency part closest to the pin”. It also explains the counter-intuitive result that removing capacitors can improve a PDN: a bank of identical parts in parallel produces a parallel resonance where their collective inductance meets the plane capacitance, and that peak can exceed the target impedance even though every individual part is fine.

A power–ground plane pair is often described as free decoupling capacitance, and the arithmetic supports the description only at low frequency. Capacitance goes as ε₀ε_rA/d: at a 0.1 mm gap in FR-4 that is about 37 pF/cm², so a 100 cm² pair gives 3.7 nF — less than a single 0.1 µF ceramic, but distributed and with almost no series inductance.

At 10 MHz, 3.7 nF is 4.3 Ω; at 100 MHz, 0.43 Ω. Both are above the target impedance for a core rail, which is why the plane pair cannot replace capacitors. What it does better than anything else is provide a short, wide return path, which lowers the loop area for the capacitors that are doing the work.

Above about 1 GHz the pair stops behaving as a lumped capacitance and starts behaving as a cavity. Resonant frequencies scale as roughly 150 / L GHz for a board dimension L in millimetres, so a 100 mm board has modes near 1.5 GHz and a 40 mm board near 3.75 GHz. At a mode, the impedance at some points on the pair rises sharply while other points remain low, so two decoupling capacitors a few centimetres apart can behave completely differently. Edge stitching, and in severe cases lossy edge termination, is the control — the same λ/20 arithmetic that governs via fences. Where the pair sits in the layer stack is a stack-up decision, set out in high-frequency PCB stack-up design.

Between the capacitor and the plane there is a via; between the plane and the die there is another via and a package. Each contributes inductance, and inductance is what turns a capacitor into an inductor at the frequency where it is needed.

The practical rule is to count the loop, not the component: capacitor pad → via → plane → via → die pad. That loop, not the capacitor value, sets the frequency above which the part is useless. Placing a 0.1 µF capacitor with 10 mm of trace and two long vias produces a network whose impedance peaks somewhere in the tens of megahertz — and a peak is worse than a flat higher impedance, because it is where the noise will land. Via geometry and length are covered in PCB through holes.

A ferrite bead in series with a supply is a frequency-dependent resistor, with an impedance that rises to a peak somewhere between 100 MHz and 1 GHz and then falls as the part becomes capacitive. Used to isolate one rail from another, it forms a low-pass filter with the decoupling capacitance on the far side — and that is a second-order network with a resonant peak.

The peak is the problem. A bead with 1 kΩ at 100 MHz and a few tenths of a microhenry of parasitic inductance, working into 1 µF of ceramic, resonates in the low megahertz with a Q that can reach 10 or more: the isolation at the resonant frequency is not 1 kΩ but a few ohms, and the noise is amplified rather than blocked. The standard fix is a damping resistor or a lossy capacitor in the network, or — better — a dedicated regulator for the sensitive rail instead of a bead.

Two further caveats. Beads saturate: at rated DC current, impedance often falls by half or more, so a bead specified at 1 kΩ may present 400 Ω in the circuit. And above about 1 GHz the bead is capacitive, so it provides no isolation at the frequencies where a millimetre-wave board is most exposed. Isolation at those frequencies has to come from geometry and shielding, not from a series part.

Phase-locked loops and voltage-controlled oscillators are the components most often described as “sensitive to power noise”, and the sensitivity can be quantified. A VCO has a pushing figure — a few megahertz per volt is typical — so a 10 mV ripple at 100 kHz offset shifts the carrier by about 50 kHz. The modulation index is Δf/f_m = 0.5, which puts sidebands at roughly −12 dBc relative to the carrier. That is a spurious emission that will fail a spectrum mask without anything being “wrong” with the board.

Three measures work, in order of effectiveness. A dedicated low-dropout regulator with high ripple rejection at the offset frequency — 60 dB of rejection turns 10 mV into 10 µV. A local RC or LC filter at the VCO supply pin, with the resistor sized for the current and the capacitor sized for the lowest offset of interest. And a clean reference plane under the VCO, connected to the main ground at the point where the regulator’s return current flows.

What does not work, below a few hundred megahertz, is distance. At 100 MHz the wavelength in the dielectric is 610 mm, so moving a PLL from 10 mm to 30 mm from a switching regulator changes the coupling by very little. Distance only helps when the separation is a meaningful fraction of a wavelength, which on a board means above about 1 GHz — and even then, coupling is dominated by shared planes and shared return paths rather than by line of sight.

The source article offered eleven measures. Applied as a checklist they conflict; sorted by mechanism, about half survive.

The pattern is consistent: the recommendations that describe a geometry survive, the ones that borrow a measure from another domain do not, and the ones phrased as “keep things apart” usually fail because separation is not a mechanism below a wavelength.

A power delivery network can be measured directly, and doing so ends most of the discussion. The standard method is the two-port shunt-through measurement: a vector network analyser with port 1 across the rail and port 2 across the ground, a coaxial injector, and a calibration to the measurement plane. The result is |Z| against frequency, which is the same curve the target impedance is drawn on.

Three features are worth looking for. A peak above the target line identifies a parallel resonance between capacitor banks, which is fixed by changing values or adding damping rather than by adding parts. A rising impedance at high frequency identifies mounting inductance, which is fixed by placement and via count. And a flat low impedance that nonetheless produces noise at the die identifies the package, which no board change will fix.

Where a VNA is not available, a simpler proxy works: measure the ripple at the load with a wideband probe while the load executes its worst-case step, and compare against the rail specification. That measurement cannot separate the mechanisms, but it answers the question the design was asked — whether the rail stays inside its window — and the coupon and impedance measurements in high-frequency PCB testing cover the transmission-line side of the same board.

1. Write the target impedance for every rail, with the voltage, the allowed ripple and the worst-case step. 2. Choose the plane pair spacing from the band that needs it — 0.1 mm or less where the pair must carry current between 10 and 100 MHz — and check the first cavity mode against the highest clock harmonic. 3. Place capacitors by frequency, not by pin count: bulk at the regulator, ceramics distributed, the smallest values closest to the pins, every connection by via to the plane. 4. Check the loop for each capacitor, including the return via, and count the inductance rather than the capacitance. 5. Measure the finished board and compare with the target curve, then decide whether the remaining gap is a board problem or a package problem.

Step five is the one that is usually skipped, and it is the only one that prevents the next board from repeating the same argument. A PDN measurement takes an hour and produces a curve that either meets the target line or shows exactly which band does not. Steps two and three are also where the fabricator’s own tolerances enter, since the plane spacing and the dielectric height are pressed values rather than drawn ones — see impedance control in manufacturing.

How can power supply noise interference on high-frequency PCBs be resolved: by turning it into an impedance specification and then working along the frequency axis. The target impedance is V × ripple % / ΔI, which is 165 mΩ for a 3.3 V rail stepping 1 A and 5 mΩ for a 1.0 V rail stepping 10 A. Below 1 MHz the regulator and bulk capacitance are in control; between 1 and 50 MHz it is ceramics, limited by mounting inductance rather than by value; above 50 MHz the plane pair and the package take over, and above 1 GHz nothing on the board can help.

The three structures that cause most of the trouble are all small: the via and trace inductance between a capacitor and its plane, which turns 0.1 µF into an inductor at 17 MHz; the parallel resonance between capacitor banks, which produces a peak that no single part explains; and the ferrite bead used as an isolator, which forms a resonant tank with the capacitance it is supposed to protect. Each has a measurement that identifies it and a geometry that fixes it.

XCE PCB builds the board side of this: 2 to 72 layers, plane pairs down to 0.1 mm, 0.127 mm cores, impedance held to ±10 % with coupon TDR, registration to ±25 µm per lamination cycle, panels to 600×1200 mm, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. The plane and cavity arithmetic is shared with EMC in layer-up design and with impedance control.