In high-frequency PCB design, electromagnetic compatibility (EMC) issues primarily stem from compromises in signal integrity and power integrity, such as crosstalk, radiated interference, and power supply noise. EMC issues can be effectively addressed through measures such as optimizing the layer stackup, implementing proper layout and routing, and enhancing shielding and filtering. The following are specific solutions:

I. Optimizing the Layer Stackup: Mitigating EMC Risks at the Source

Tightly Coupled Reference Planes

Signal-to-Ground Adjacent Layout: The high-frequency signal layer (e.g., the Top layer) must be immediately adjacent to a continuous ground plane (GND) below it, forming a “signal-to-ground” coupling structure. This shortens the signal return path and reduces radiation.

Example: In a 4-layer board, Top layer (signal) → GND layer (spacing ≤ 0.2 mm) → PWR layer → Bottom layer (signal). The GND layer isolates high-frequency signals from power supply noise.

Power-Ground Pairing Design: The power layer (PWR) and ground layer (GND) must be placed adjacent to each other, with a recommended interlayer dielectric thickness of ≤0.3 mm, to form a low-impedance decoupling capacitor that suppresses power supply ripple.

Example: In a 6-layer board, the PWR layer is paired with the GND layer, with an interlayer dielectric thickness of 0.2 mm, which reduces the interference of power supply noise on the signal.

Avoid Direct Adjacency of Signal Layers

Adjacent signal layers are prone to crosstalk and must be isolated by ground or power layers. High-frequency signal layers should be sandwiched between reference planes to form a “shielded cavity.”

Example: In an 8-layer board, Top layer (signal) → GND layer → Signal1 layer (auxiliary signal) → PWR layer → GND layer → Signal2 layer (auxiliary signal) → PWR layer → Bottom layer (signal), with signal layers isolated by GND layers.

Multi-Layer Shielding Design

Add dedicated shielding layers above and below critical signal layers (such as RF signal layers), such as metallized via fences or embedded metal shielding layers, to block electromagnetic radiation paths.

Example: In a millimeter-wave radar PCB, GND layers are placed above and below the RF signal layer and connected via dense vias (spacing ≤ 0.5 mm) to create a Faraday cage effect.

II. Layout and Routing Optimization: Reducing Electromagnetic Coupling and Radiation

Prioritize Key Signal Placement

High-frequency signals (such as RF differential pairs and clock signals) should be placed on the top layer (e.g., Top layer) with the GND layer immediately below, avoiding crossing with other signal layers.

Low-speed signals (such as I2C and SPI) should be placed on inner layers (e.g., Signal layer) and isolated from high-frequency interference by the GND layer.

Differential Signal Design

Differential pairs must be strictly equal in length (length difference ≤ 50 mil) with a constant spacing (e.g., 0.2 mm) to cancel out common-mode noise.

GND vias should be placed around the differential pairs (spacing ≤ λ/20, where λ is the signal wavelength) to form a shielding ring.

Via Optimization

Blind/Buried Via Technology: Reduces impedance discontinuities during interlayer transmission and lowers radiation.

Ground Vias: Add GND vias adjacent to signal vias (spacing ≤ 0.5 mm) to form a “signal via-ground via” shielding structure.

Back Drilling of Vias: Perform back drilling on high-speed signal vias to eliminate the stub effect and reduce reflections and radiation.

Power Integrity Design

Decoupling Capacitor Placement: Place small capacitors in 0402/0201 packages (e.g., 0.1μF, 10nF) next to the power pins of high-frequency chips, close to the chip pins (spacing ≤ 0.5mm), to quickly suppress power supply noise.

Power Plane Segmentation: For multi-power-supply systems, isolate different power domains using GND layers to prevent power supply noise coupling.

III. Shielding and Filtering: Blocking the Propagation of Electromagnetic Interference

Shielding Layer Design

Metallized Via Fence: Arrange dense GND vias (spacing ≤ 0.5 mm) around critical signal areas to form an electromagnetic shielding wall.

Embedded Metal Shielding Layer: Embed metal foil (e.g., copper foil) within the PCB inner layers and connect it to GND via vias to block high-frequency radiation.

Shielding Enclosure Design: Install metal shielding enclosures around sensitive components (such as RF modules) and ground them using spring clips or conductive adhesive.

Filter Circuit Design

Power Supply Filtering: Add a π-type filter (such as an inductor-capacitor combination) at the power supply input to suppress high-frequency noise from entering the system.

Signal Filtering: Add common-mode chokes (CMChokes) to high-frequency signal lines (e.g., USB, HDMI) to filter out common-mode noise.

Ferrite Bead Application: Place ferrite beads in series on critical signal lines (e.g., replacing 0Ω resistors) to absorb high-frequency noise.

IV. Material and Process Control: Reducing EMC Risks

Selection of Low-Loss Materials

Prioritize laminates with low dielectric constant (Dk) and low loss factor (Df) (e.g., Rogers RO4350B, Taconic TLY-5) to reduce signal transmission loss and radiation.

Avoid using standard FR4 (Df ≈ 0.02), as its loss increases significantly at frequencies above GHz.

Impedance Control and Consistency

Use professional tools (such as Polar SI9000) to accurately calculate trace width, spacing, and dielectric thickness to ensure target impedance (e.g., 50Ω single-ended, 100Ω differential).

Account for the impact of the solder mask: The solder mask covers the transmission lines, increasing the equivalent Dk; therefore, a margin must be factored into calculations (e.g., for a 50Ω design, the actual trace width should be reduced by 0.02mm).

Lamination Process Control

During lamination, control temperature, pressure, and dwell time to ensure uniformity of dielectric thickness (deviation ≤ ±0.01mm) and avoid impedance fluctuations.

Avoid signal reflection and radiation caused by interlayer dielectric thickness deviations.

V. Simulation and Test Verification: Ensuring EMC Compliance

Simulation Verification

Use software (such as Ansys HFSS or CST) to simulate signal radiation field strength along transmission lines and optimize shielding design (e.g., increasing via density, adjusting shield layer position).

Simulate the impact of power supply noise on signals to optimize the layout of decoupling capacitors and the segmentation of power planes.

Impedance Testing

After lamination and etching, test 5% of the samples for impedance. If deviations exceed ±5%, halt production to analyze the cause and adjust the process.

Use a Time Domain Reflectometer (TDR) to measure the actual impedance of traces on test strips to verify compliance with design tolerances.

EMC Testing

Radiated Emission Testing: Verify that PCB radiated emissions comply with standards (e.g., CISPR 32, FCC Part 15), and optimize shielding design (e.g., adding shielding covers, adjusting via spacing).

Conducted Emission Testing: Verify that power supply noise complies with standards (e.g., EN 55032), and optimize filter circuit design (e.g., adding ferrite beads, adjusting capacitance values).