How to Address Electromagnetic Compatibility in High-Frequency PCB Layer-Up Design

To address electromagnetic compatibility in a high-frequency PCB, the layer-up has to be settled before the routing is drawn, because every EMC measure is a wavelength-scale structure: useful when its dimensions are small against the wavelength of the emission, useless when they are not. A 0.5 mm via pitch is a wall at 10 GHz and a picket fence at 77 GHz. This article takes the layer-up in the order that matters — reference planes, plane pairing, plane integrity, fence pitch, layer transitions — quantifies each with the frequency at which it starts and stops working, and then corrects four measures that are widely repeated and no longer true above about 100 MHz.

An emission is radiated when a structure is electrically large: when its dimensions approach a meaningful fraction of the wavelength. The same 20 mm loop that is invisible at 100 MHz, where the wavelength is 3 m, is a efficient antenna at 3 GHz, where the wavelength is 100 mm. This is why EMC measures cannot be listed as a set of good practices: each one has a frequency range, and outside it the measure either does nothing or makes the problem worse.

Read the λ/20 column as a manufacturing specification. It is the pitch at which a row of vias, a seam or a row of decoupling capacitors stops behaving as a continuous wall and starts behaving as a set of discrete scatterers. At 10 GHz that means 0.9 mm; at 28 GHz, 0.33 mm, which is below the drill-to-drill spacing of most conventional processes and forces a different strategy — a thinner dielectric, edge-plated cavities, or accepting a lower isolation and fixing the source instead.

The primary EMC decision in a layer-up is not how many planes there are but whether each signal layer has a reference plane immediately adjacent to it — and whether that plane is ground. A return current flows in the plane directly beneath its trace, and the fraction of the field that escapes the plane is set by the dielectric height. At 10 GHz, most of the return current is confined to a band roughly three dielectric heights wide: 0.76 mm on a 0.254 mm build, 1.5 mm on 0.508 mm. A plane that is far away, or interrupted, cannot confine it, and the residual field is what radiates.

This is why the four-layer “top–ground–power–bottom” stack is a compromise rather than a recommendation: the bottom layer references the power plane, which carries switching current. For a control board that is acceptable. For an RF or high-speed layer it is not, because the return current shares a conductor with the current that is causing the noise. The arithmetic of which layer count can support which reference structure is in high-frequency PCB stack-up design, and the physical role of each layer in PCB structural layers.

A practical test at review time: take the layer-up and draw, for every signal layer, the plane it references and the distance. If any layer references a plane two layers away, or references a plane that is split, that layer will be the one that fails the chamber.

The advice to place power and ground adjacent with a small dielectric gap is correct in direction and usually overstated in effect. The capacitance of a plane pair is straightforward: C = ε₀ε_rA/d, which for FR-4 at 0.1 mm gap gives about 37 pF per square centimetre, or 3.7 nF for a 100 cm² pair. That is a real capacitor, but a small one, and above roughly 100 MHz its own spreading inductance dominates.

Two consequences. First, a plane pair cannot replace decoupling capacitors at the frequencies where they are needed; it can only reduce the loop area that those capacitors have to work with. Second, on a large board the pair behaves as a resonant cavity, with modes at roughly 150 / L GHz for a dimension L in millimetres — a 100 mm board has its first mode near 1.5 GHz. Energy injected into that cavity at a mode frequency circulates and radiates from the edges, which is why edge stitching and, in severe cases, lossy edge treatment exist.

The instruction to separate analog and digital grounds by cutting the plane is the most durable piece of EMC folklore and the most reliably counter-productive above about 1 MHz. A cut in the reference plane forces the return current to detour around it, and the detour is a loop. On a 10 GHz board the return current wants to stay within 0.76 mm of its trace; a slot directly beneath the trace turns that 0.76 mm band into a loop of the slot’s length, which is exactly the structure that radiates.

Where two functions must be separated, the mechanism is placement and plane assignment, not cutting: keep the analogue circuitry in one region, give it its own continuous ground area on the same plane, and route the digital signals so their return current does not have to cross into the analogue region. If a controlled crossing is unavoidable, the return path must be provided locally — by a stitching capacitor or a via to the reference of the other side — not by a ferrite bead in series with a plane.

The series ferrite bead between two ground regions is a special case that deserves its own warning. A bead with 100 Ω at 100 MHz and a few microhenries of parasitic inductance forms a resonant tank with the plane capacitance on either side; at the resonant frequency the isolation becomes an impedance peak several times higher than either side, and above a gigahertz the bead is capacitive and provides no isolation at all. The measure works in the 1–30 MHz region where it was invented, and is a liability above it.

Via fences around RF runs and along board edges work by raising the cutoff frequency of the parallel-plate waveguide formed by two planes. The pitch must be small against the wavelength in the dielectric; λ/20 is the conventional threshold, and the table in the first section converts it into millimetres. A fence at a fixed 0.5 mm is therefore correct at 10 GHz, marginal at 20 GHz and useless at 77 GHz.

Three practical points follow. The vias must connect the planes that form the cavity — a fence that stops at an inner plane does not close the cavity between the outer layers. The fence must be continuous around the structure; a gap of a few millimetres is an aperture that radiates at the frequency whose half-wavelength matches the gap. And the fence should follow the edge of the RF region rather than the edge of the board, because the energy that matters is where the field is, not where the outline is.

Where the pitch needed is below the process limit — 0.13 mm at 77 GHz, which no conventional drill can hold at reasonable cost — the alternative is to reduce the dielectric height so that the field never reaches a wide cavity, or to move the RF section to a separate thin laminate and connect it by a controlled launch. Both are layer-up decisions, taken before layout.

When a signal changes layers, its return current must change planes, and the only low-impedance path between planes at high frequency is a via placed close to the signal via. Without it, the return current finds a path through the nearest decoupling capacitor or through the plane edges, and that path is both long and shared — shared with other signals, which is common-impedance coupling, and long, which is radiation.

The distance that counts is not the pitch of the stitching field but the distance from the signal via to its return via. A useful working number is that the loop formed by the two vias should stay under λ/20 at the highest frequency: 0.9 mm at 10 GHz, 0.33 mm at 28 GHz. Placing a return via within 0.5 mm of every signal via satisfies this to about 18 GHz. Beyond that, the transition itself has to be designed as a structure — a short back-drilled via with an adjacent ground via on each side, or a coaxial launch.

The stub is the other half of the transition. A 1.6 mm through via resonates near 23 GHz in FR-4 and 32 GHz in PTFE; at resonance it stops transmitting and starts reflecting, which is both an insertion-loss and an EMC problem. Back-drilling removes most of the stub and is the standard answer above 20 GHz; the arithmetic is in PCB through holes.

A metal can around an RF section is an effective shield only if its seams and its grounding are electrically short. The can itself forms a cavity whose resonant frequencies are set by its largest dimension — about 150 / L GHz for L in millimetres — so a 20 mm can resonates at 7.5 GHz, and a 10 mm can at 15 GHz. At resonance the field inside is amplified, the seam currents are maximum, and the shield radiates more than the bare board did.

The practical controls are three. Ground the can at a pitch below λ/20 along every edge, using the board’s own via fence rather than relying on clip contact. Keep the largest internal dimension from coinciding with a harmonic of any clock or LO. And where a resonance cannot be avoided, place an absorbing material on the inside of the lid — a lossy absorber changes the cavity Q and removes the amplification, at the cost of a few tenths of a decibel of wanted signal.

The same arithmetic applies to the board-level shield: a shield that is grounded at four corners only has seam lengths of half the can perimeter, which is a half-wave antenna at a few hundred megahertz. This is why the fix for a shield that “does not work” is almost always more ground vias rather than a thicker can.

Filters are the part of EMC work where component parasitics decide the outcome, and where the frequency range of each part is routinely ignored.

The general rule is that a filter made of lumped parts stops working when its own parasitics become comparable to the impedance it was meant to present. Above 1 GHz, the reliable measures are geometric: keep the loop small, keep the reference continuous, and move the radiation source rather than filtering after it.

A differential pair radiates little when it is balanced, because the two conductors carry equal and opposite currents and their fields cancel at a distance. The cancellation is only as good as the balance, and the most common source of imbalance on a PCB is length mismatch between the two lines.

On a microstrip with ε_eff near 2.7, 1 mm of length is about 5.5 ps. At 10 GHz, where the period is 100 ps, a 1 mm mismatch is a 5.5 % phase error, which converts roughly 5 % of the differential signal into common mode — about −26 dB of mode conversion, in the range where it starts to matter for a strict emission limit. The same 1 mm at 1 GHz is 0.55 % and harmless. Length matching is therefore a frequency-dependent requirement, not a fixed 5 mil rule.

Two further structures matter. The pair must not be routed over a plane split, because the return current of each line then takes a different path and the balance is destroyed regardless of length. And the pair’s spacing must be held through connectors and via fields; a 0.3 mm gap that opens to 0.8 mm for a few millimetres changes the local impedance and radiates as a small dipole at the transition.

Low-loss laminate is often sold as an EMC measure. It is not one. Radiated emission is set by the current distribution and the geometry of the radiators — loop area, cable common-mode current, cavity modes — and the dielectric loss only attenuates the wave as it travels along the line. On a 20 mm trace at 10 GHz, the difference between 1.08 dB/in and 0.13 dB/in is about 0.75 dB, which changes the emission by less than a decibel. What the laminate does change is the impedance tolerance, and a badly controlled impedance reflects more, which can increase radiation from the discontinuity.

Surface finish matters more than most EMC documents admit, for a different reason: it changes the loss of the outermost conductor, and it changes the contact resistance of every ground connection. A finish that oxidises in storage raises the impedance of the shield-to-ground path at every clip and screw, and that path is part of the shield. The finish windows and their failure modes are in surface treatment on high-frequency PCB, and the mask, which is the other dielectric layer that nobody models, in solder mask on high-frequency PCB.

EMC debug fails most often because the measurement does not distinguish between mechanisms. A radiated emission at 750 MHz can come from a cable common-mode current, a board edge, a shield seam or a power plane mode, and the four have completely different fixes. A near-field scan with a small loop separates them in minutes.

The corresponding acceptance measurements are conducted emission on the power port and radiated emission in a chamber, assessed against the limits in the applicable standard — for information technology equipment, CISPR 32 Class B radiated limits are 30 dBµV/m from 30 to 230 MHz and 37 dBµV/m from 230 MHz to 1 GHz at 10 m, with a separate set of limits above 1 GHz. The impedance and coupon measurements that support this work are described in high-frequency PCB testing.

1. Every signal layer references an adjacent plane, and the distance is stated in millimetres. 2. No signal layer references power unless the plane pair is 0.1 mm or closer. 3. No plane split under any trace that crosses it; if a crossing exists, a stitching capacitor is placed within λ/20. 4. Edge stitching pitch is stated as a frequency, not only as a distance. 5. Every layer transition has a return via within 0.5 mm. 6. Via stub length is specified and back-drilling is called out where the stub would resonate in band. 7. Power plane pairs are close enough to be useful and far enough from the board edge to avoid a low-order cavity mode. 8. Shielding can dimensions avoid clock harmonics, and seam grounding is at λ/20. 9. Mask is pulled back from RF traces and from ground contact areas. 10. The layer-up names the frequency at which each measure stops working, so the review can check the claim rather than the intention.

Item ten is the one that changes the conversation. A layer-up that says “ground vias every 0.5 mm” invites agreement; a layer-up that says “ground vias every 0.5 mm, valid to 18 GHz, above which the fence is discontinuous” invites a decision.

To address electromagnetic compatibility in a high-frequency layer-up, work in wavelength order. At 10 GHz the wavelength in the dielectric is 18 mm and λ/20 is 0.9 mm; at 28 GHz the numbers are 6.6 mm and 0.33 mm. Every structure in the layer-up should be checked against those numbers: plane adjacency, fence pitch, return-via distance, seam spacing, can dimensions.

Four measures commonly recommended for EMC are obsolete above about 100 MHz, and should be replaced rather than repeated: splitting the ground plane (replace with functional partitioning on a continuous plane), joining two grounds through a ferrite bead (replace with a continuous plane and local stitching), treating the power–ground pair as a decoupling capacitor (replace with explicit capacitors plus a close plane pair for loop area only), and relying on laminate loss to reduce emissions (replace with loop-area and common-mode control).

XCE PCB supports this work at the layer-up stage: 2 to 72 layers, PTFE and hydrocarbon laminates with 0.127 mm cores, impedance held to ±10 % with coupon TDR, registration to ±25 µm per cycle, panels to 600×1200 mm, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. The impedance arithmetic that underpins the plane and via rules is in impedance control and in the concepts of electricity in a PCB.