To understand the bottlenecks in AI hardware development, one cannot focus solely on chips. Think of the entire system as an information-dense megacity: chips are the “brains,” while the high-frequency printed circuit boards that carry them are the interconnected “highway network” and “power grid” linking all these brains. Currently, the AI computing race is placing unprecedented pressure on this “road network,” with the key challenges concentrated in the following three areas:

The First Hurdle: The Physical Limits of Materials
This is the most fundamental challenge. As data transfer rates within AI servers advance from tens of gigabits per second to 112Gbps or even 224Gbps, traditional PCB base materials are akin to an old road covered in gravel, causing severe “bumps” and loss for high-speed signals.

1. The “Road Surface” Must Be Smoother: High-frequency signals travel along the surface of copper conductors. Therefore, the rougher the copper foil surface, the greater the signal loss. To address this, the industry is transitioning from standard copper foil to HVLP copper foil, which features a mirror-smooth surface to minimize transmission loss.
2. The “Roadbed” Must Be More Stable: The dielectric constant and dissipation factor of the insulating and supporting dielectric materials must be extremely low and stable. Think of Dk as the resistance to signal propagation and Df as the energy loss. Just as one cannot run fast in mud, materials with high values slow down and weaken signals. Consequently, new substrate materials based on high-performance resins like polyphenylene ether are replacing traditional ones.

The Second Hurdle: The Maze of Design Complexity
Using new materials is just the foundation. Packing dozens of layers containing kilometers of fine circuits into a board the size of a lunchbox, while ensuring all signals operate without interference, leads to an exponential increase in design complexity.

1. The Precise “Skyscraper” of Multilayer Stacking: AI server motherboards have evolved from over a dozen layers to 30, 40, or even more layers. The alignment accuracy between each layer must be at the micrometer level; even a slight misalignment can cause signal reflection or short circuits. Simultaneously, such high layer counts create immense thermal management pressure. With chip power consumption often reaching hundreds of watts, failure to dissipate heat promptly can lead to system failure.
2. The “Stable Dam” of Power Supply: When AI chips unleash bursts of computing power, it’s akin to a pulsed impact on the power grid. If the power delivery network cannot respond instantly or maintain stable voltage, the chip may stall. Therefore, power integrity design has become critical. This requires dedicated power layers and complex filtering to ensure current flows like a calm lake rather than turbulent waves.

The Third Hurdle: The Real-World Bottlenecks of Manufacturing and Supply
Even with a perfect design, manufacturing it with high yield and low cost, and establishing a stable supply chain, presents another significant challenge. Globally, only a handful of manufacturers can stably mass-produce high-end PCBs for AI servers.

1. “Chokepoint” Upstream Materials: Core materials such as high-end HVLP copper foil and low-loss resins have long been dominated in terms of technology and patents by a few foreign companies, leading to tight supply and high costs.
2. The “Mount Everest” of Process: Manufacturing high-layer-count PCBs with microvias and fine lines involves hundreds of processes like laser drilling, precision lamination, and plating. For instance, laser drilling energy must be controlled with microjoule-level precision, or it will fail. This demands massive capital investment and long-term technological accumulation, creating an extremely high industry barrier.

Future Directions for Breakthroughs
In response to these challenges, the industry is exploring paths forward:

• Using AI to Design AI Hardware: Generative AI is being integrated into PCB design tools. It can automate routing optimization and predict signal bottlenecks, drastically shortening design cycles and improving design efficiency and success rates from the outset.
• Integrating with Chip Packaging: With the advancement of chip packaging technologies, the boundary between PCBs and chip substrates is blurring. In the future, some ultra-high-speed, high-density interconnection tasks may be handled by silicon interposers within the package, thereby alleviating the extreme demands on the PCB.

In summary, high-frequency PCBs are a critical bottleneck in the current evolution of AI hardware. The three interconnected challenges—low-loss materials, ultra-high-complexity design, and advanced manufacturing processes—must be overcome. Breaking through these bottlenecks requires not only advancements in materials science and precision manufacturing but also potential innovations in system architecture and design methodology. The intensity and significance of this upgrade race are on par with the competition in chip development itself.