PCBA Manufacturing Process: Seven Stages and the Process Window at Each One

Most descriptions of the PCBA process list the seven stages and stop, which leaves the reader knowing the sequence but not the numbers that decide whether the assembly passes. This one keeps the sequence and adds the window: stencil area ratio, paste volume tolerance, reflow time above liquidus, wave contact time, ionic contamination limit. It closes with the constraint that makes RF assemblies different — what a 240 °C excursion does to a PTFE stack.

The sequence is fixed: incoming inspection, paste printing, placement, reflow, through-hole soldering, cleaning, test. What varies between a good and a mediocre line is whether each stage has a measurable window and an instrument that checks it before the next stage covers the evidence.

Two very different inputs arrive at once and both need checking. The bare board should come with electrical test data and a finish report; the components should come with a moisture sensitivity level and a date code.

Moisture is the item that gets skipped. Plastic packages absorb water, and water turns to steam at reflow, which is how popcorning and internal delamination happen. MSL 3 parts have a floor life of 168 hours out of the dry pack; beyond that they need baking at the manufacturer’s schedule, not a guess. On boards carrying PTFE laminates there is a companion rule: the laminate itself absorbs very little (5880 is 0.02 %, TLY-5 the same), so a bare RF board does not need the FR-4 pre-bake — but the assembly still has to be dried if it has been stored in humidity, because the components dominate the moisture budget.

Roughly half of all solder defects originate at printing, and the reason is geometric: the amount of paste deposited is set by the stencil aperture, and aperture behaviour changes with the ratio of opening area to wall area.

The rules that follow from the table: a 0.4 mm pitch device needs a 0.10–0.12 mm stencil and a stepped or laser-cut aperture, not a compromise thickness that also serves a 0.8 mm connector. And squeegee pressure, speed and separation speed are per-product settings, not machine defaults — the same stencil on two lines with different pressure gives two different deposit volumes.

Modern chip shooters place at ±0.05 mm and fine-pitch heads at ±0.025 mm, which is well inside the tolerance of most pads. Placement defects therefore tend to come from setup rather than capability: wrong feeder, wrong rotation, a nozzle that picked the part by its body instead of its centre, or a board that moved because it was not supported between tooling pins.

The check that catches these is a first-article inspection before reflow, on the first board of every run — not after. Once the board is reflowed, a rotated part is a rework operation instead of a placement correction.

For SAC305 (melting range starting at 217 °C) the profile has four numbers that matter, and all four should be on the process sheet:

Two caveats that are usually omitted. First, the profile is measured on the product with thermocouples attached to the worst-case locations — a large thermal mass, a shadowed area under a connector — not on a bare test coupon. Second, warpage: large BGA packages and thin boards interact, and the acceptance figure is normally quoted as a percentage of package diagonal (0.75 % is a common ceiling) measured at reflow temperature, not at room temperature.

Wave soldering is the traditional answer and it is no longer the default, because most boards are mixed-technology: a wave would re-melt and disturb the SMD side. The three routes, and when each applies:

• Wave soldering — boards with through-hole parts only, or SMD confined to the side that does not face the wave. Contact 3–5 s at 250–260 °C with preheat at 90–120 °C; barrel fill is the acceptance criterion, not wetting.
• Selective soldering — the usual choice for mixed boards: a nozzle delivers solder to individual THT sites, so the SMD side is never immersed. Slower per joint, precise, and it handles connectors that a wave would shadow.
• Pin-in-paste (through-hole reflow) — paste printed into the hole and reflowed with the SMD side in one pass. Cheapest when it works, but it needs hole-to-pin clearance and paste volume calculated per connector; it fails on thick boards and on holes with large thermal mass.

For a high-layer-count or heavy-copper board, pin-in-paste often fails for a second reason: the hole absorbs heat from the barrel, and the paste at the bottom of a 3.2 mm hole does not reach liquidus before the top starts to cool.

Cleaning removes flux residue and ionic contamination. It does not remove excess solder — that is rework — and it should not be applied to a no-clean process, where the residue is designed to stay and washing can drive contamination under components instead of off the board.

The acceptance figure is ionic contamination, usually tested by resistivity of solvent extract and reported as micrograms of NaCl equivalent per square centimetre. The common limit for high-reliability work is 1.56 µg/cm²; consumer work often accepts 3–4. The number matters because ionic residue plus moisture plus bias is the mechanism behind electrochemical migration — the failure that appears weeks after the board passes every electrical test.

Test is a ladder, not a single gate, and each rung sees something the others cannot. The detail belongs to the inspection and quality-control article; the one-line version: SPI checks paste before placement, AOI checks appearance after reflow, X-ray checks what is hidden (BGA, QFN thermal pads), ICT checks nets and component values, FCT checks function, and reliability testing checks the ones that will fail in a year.

The ordering rule is that each gate must come before the stage that makes its evidence inaccessible. AOI after conformal coating is decoration. X-ray after the assembly is potted is impossible.

Assembling a high-frequency board adds one constraint that does not appear on general PCBA process sheets: the laminate moves far more in Z than FR-4 does, and reflow is the largest thermal excursion the board will ever see.

Across a reflow from 25 °C to 240 °C, a 1.6 mm board expands in Z by roughly:

Eighty microns of Z movement pulls the plated barrel against copper that expands by about 6 µm over the same span. The barrel survives by stretching, which is why high-ductility plating (≥20 % elongation) and an aspect ratio held to 6:1 matter more on a PTFE board than on FR-4 — and why assemblies on these laminates are usually limited to one or two reflow cycles, with rework planned rather than improvised.

Two further RF-specific assembly notes. Ground vias under a die-attach or a connector are part of the RF return path, so rework that removes and re-inserts a connector changes the ground geometry. And solder mask on PTFE adheres less well than on epoxy, so the mask design should keep it off pads and away from connector interfaces rather than relying on it to dam fine features.

The PCBA process is seven stages with a window at each, and the windows are the part worth writing down: area ratio above 0.66, paste volume within ±20 %, 45–90 s above liquidus at a 235–245 °C peak, 3–5 s of wave contact, ionic contamination under 1.56 µg/cm². On RF laminates add one more: budget the Z-axis movement, keep the aspect ratio down and the plating ductile, and treat reflow cycles as a finite resource.

The fabrication side of that constraint is covered in the high-frequency manufacturing process guide, in the multilayer 5880 processing article and in the 5880 plus FR-4 lamination article; what matters at assembly is that the barrel budget was already spent upstream.

XCE PCB builds the bare board and supports assembly on the same floor — 2–72 layers, impedance to ±10 %, 5,000 m² of production space and 80+ engineers, with PTFE-qualified processing and samples in as fast as 24 hours.