PCBA Quality Control: Five Inspection Gates and What Each One Can Actually See

The assembly process is described in one article; how you know it worked is a second, and it is the second that decides whether a defect reaches a customer. Each inspection gate has a visibility limit — SPI sees paste, AOI sees surfaces, X-ray sees hidden joints, ICT sees nets, functional test sees behaviour — and a quality plan is the arrangement of those limits so that nothing falls between them.

Five gates cover a PCBA build. The useful way to read them is not by equipment cost but by what each one is blind to, because that is what the next gate has to catch.

The ordering rule follows from the last column of each row: a gate must run before the stage that makes its evidence inaccessible. X-ray after potting is impossible; AOI after conformal coating inspects the coating. This is also why the process article puts test last while the quality plan starts measuring at the printer — the sequence on the floor and the sequence of evidence are not the same sequence.

Every judgement above is made against a standard, and the standard has classes. IPC-A-610 is the usual acceptance document for assemblies; IPC J-STD-001 governs the process requirements that produce them. Class 2 is the default for commercial product: functional, with visible imperfections tolerated. Class 3 adds criteria for products where uninterrupted service is required — typically medical, aerospace and defence.

The difference is measurable, not nominal. Class 3 tightens fillet requirements, restricts voiding, restricts side overhang on chip components, and in some cases requires a higher barrel fill on through-hole joints. Two consequences worth stating to a customer: the same assembly can be acceptable at Class 2 and rejected at Class 3, and quoting “IPC-A-610 compliant” without a class is not a specification.

Naming the defect is easy; naming the stage that caused it is what shortens the loop. The mapping below is the practical one:

Head-in-pillow deserves the extra line because it defeats the standard gate. The joint is mechanically touching and electrically connected at room temperature, X-ray shows a ball in the right place, ICT passes. It fails later under thermal cycling. The only reliable detections are cross-sectioning sample assemblies and monitoring warpage at reflow temperature — which is why large, thin packages get a warpage requirement in the first place.

The planning implication: test coverage is a design decision made when test points and boundary-scan chains are placed, not a manufacturing decision made afterwards. A board with no test points and no JTAG chain gets AOI and FCT and nothing in between — which is workable for a simple assembly and inadequate for a dense one.

“Reliability tested” means nothing without the conditions. The four that appear most often, with the parameters that should accompany them:

• Thermal cycling — commonly −40 to +125 °C, 1–2 cycles per hour, 500–1000 cycles, monitored for resistance drift rather than only for failure at the end.
• Damp heat — 85 °C / 85 % RH for 500–1000 h, which is the test that finds ionic residue and coating defects.
• Vibration — sine sweep or random per the product’s service environment; the failure mode is usually a heavy component’s solder joint, not the board.
• Thermal shock — liquid-to-liquid, −40 to +125 °C, which is far more severe than air cycling and is used where the service profile justifies it.

On high-frequency assemblies there is a fifth consideration that general quality plans miss: the RF performance itself drifts. A board can pass every electrical and visual gate and still fail its insertion-loss or return-loss specification after reflow, because laminate Dk shifts slightly with the thermal history and because connector seating changes the launch geometry. That is why RF builds are usually accepted against coupon S-parameters and a first-article RF measurement, in addition to the standard gates.

Traceability is not paperwork for its own sake; it is what makes a containment possible when a defect appears three months later. The minimum set: laminate lot and date code, paste lot, component date codes by reel, reflow profile file per run, SPI and AOI results per serial number, X-ray images for area-array parts, and the test log.

Two metrics justify the effort. DPMO (defects per million opportunities) normalises across products of different complexity, so a trend line means something; a mature SMT line typically runs in the tens, and anything in the hundreds is a process asking to be investigated. First-pass yield separates process quality from rework skill — a line with 99 % final yield and 92 % first-pass yield is hiding a process problem behind a rework bench.

• Print: SPI on the first board, stencil and squeegee settings recorded against the drawing.
• Placement: first-article visual before reflow, all polarities and rotations, all fine-pitch parts.
• Reflow: thermocouple profile on the assembly at worst-case mass, filed per run.
• Inspection: AOI programme validated against a known-good and a known-bad board; X-ray on every area-array device at first article and sampled thereafter.
• Electrical: ICT or flying probe coverage report, listing which nets are untested and why.
• Cleanliness: ionic contamination result for the first article if the process is water-clean.
• RF (where applicable): coupon S-parameters and a first-article measurement against the specification.
• Record: lot codes, profile file, inspection data and test log filed against the serial or lot.

The process these gates sit on — the seven stages with their windows — is described in the PCBA manufacturing process article, which is the companion to this one rather than a duplicate.

Quality control on a PCBA build is an arrangement of blind spots. SPI covers paste, AOI covers surfaces, X-ray covers hidden volume, ICT covers nets, functional test covers behaviour — and each is silent about the next one’s territory. Write the plan around the gaps, state the acceptance class explicitly, and keep the RF-specific gate (coupon and first-article S-parameters) separate from the general electrical gates, because it is measuring something none of the others can see.

Two measurement subjects sit upstream of these gates and are worth reading alongside: impedance control for the coupon side, and bare-board testing for what a fabricator can and cannot certify before assembly; hole types and barrel fill explains the X-ray criterion applied to through holes.

XCE PCB runs bare-board fabrication and assembly under one quality system: impedance held to ±10 %, IPC-A-610 acceptance at the class specified by the customer, 5,000 m² of production space and 80+ engineers, with 2–72 layer capability and samples in as fast as 24 hours.