Impedance Control in High-Frequency PCB Manufacturing: The Loop, Not the Formula

Every article on impedance control explains that Z depends on width, dielectric height and Dk, and stops there. That part is not where boards fail. They fail in the loop that is supposed to prove the number: a coupon that does not represent the product, a TDR whose rise time cannot resolve the discontinuity, a measurement taken before the mask went on, and a corrective action that adjusts the wrong knob. This is the process side of impedance control — what to measure, how precisely, and what to change when the number comes back wrong.

The design-side arithmetic is settled: microstrip and stripline impedance follow width, dielectric height, copper thickness and Dk, and any field solver will produce a number to three decimal places. The uncertainty is not in the equation, it is in the four inputs — and in whether the measurement that closes the loop is measuring what the design assumed.

A useful way to see it is that impedance control has two halves that meet at a coupon. The design half produces a target and a tolerance. The process half produces a physical dielectric height, a physical trace width and a physical Dk, then measures the result. When the two disagree, the disagreement is almost always in the handover: the coupon, the instrument, or the point in the flow at which the measurement was taken.

This step closes out the manufacturing sequence described in the twelve-step guide, and it depends on every step before it — the press that set the height, the etch that set the width, the mask that changed the field.

A ±10% impedance spec is not a process capability; it is a budget that four contributions have to fit inside. Setting the target without the stack is how a design ends up asking for ±5% on a build whose thickness tolerance alone is ±6%.

The first row dominates, and it is the one nobody in the design office controls. That is why serious high-frequency programmes specify the pressed thickness and the laminate lot, not just the nominal core. The statistical sum of the random terms is around 6.6%, which fits a ±10% window with margin and does not fit ±5%.

A coupon is a test structure built on the same panel, in the same process, measured to infer what the product traces are doing. Three properties make it representative, and all three are routinely violated.

• Same geometry class. A 0.56 mm microstrip coupon says nothing about a 0.10 mm line: the narrow line is far more sensitive to the same absolute etch error.
• Same reference environment. A coupon with solid copper above and below is not measuring a product trace that crosses a plane split.
• Long enough to settle. The coupon must be several rise times long so the TDR trace reaches a stable plateau before the launch reflections arrive.

On 0.254 mm 4350B the effective dielectric constant is about 2.85, so a signal travels at roughly 177 mm/ns. A 100 mm coupon is 0.57 ns one way, which settles a 35 ps edge comfortably. A 10 mm coupon does not, and its reading is dominated by the launch and the probe.

Pressed thickness is not uniform across a 600 × 1200 mm press opening. Resin flow, temperature gradient and edge effects combine so that the panel edge and the panel centre differ, and a coupon placed at the edge reports a height the product never sees.

Two consequences. First, the coupon position belongs in the fabrication drawing, next to the product, on the same panel and the same press cycle — a separately pressed test panel is a different experiment. Second, when a lot comes back out of tolerance, the first question is whether the coupons and the product sat in the same place, because a 5% height difference between coupon and product is a 3% impedance difference that no process change will fix.

Time-domain reflectometry reports impedance as a function of time, and the spatial resolution of that report is set by the rise time of the launched edge, not by the sampling rate.

Resolution ≈ v × t_r / 2, where v = c / √ε_eff

A 200 ps instrument averages everything inside a 17.7 mm window. On a coupon that is fine, because the coupon is uniform. On a product trace with a connector, a stub or a plane transition inside that window, it reports a number that belongs to none of them — and it will report the same number whether the trace is right or wrong.

Every coupon measurement includes the launch: the SMA connector, the probe pads, the ground vias and the short trace between them. A launch contributes inductance in the sub-nanohenry range and shows up as a spike at the start of the TDR trace, often several ohms above the plateau, decaying over a few hundred picoseconds.

Three ways to deal with it. Use a launch characterised on a reference board and subtract it. Use a coupon long enough that the plateau is measured far from the spike. Or use a probe station with a calibrated tip and a defined reference plane. What does not work is reading the first peak and calling it the impedance, which is a common way to report a 55 Ω board as 58 Ω.

Impedance coupons are frequently measured bare, before solder mask, because that is when the shop can still change something. It is also the measurement that most often disagrees with the customer’s.

The reason is the same arithmetic as in the solder mask guide: 25 µm of mask at Dk 3.8 lowers a 50 Ω microstrip by about 3.5% on a 0.254 mm PTFE build and by 2.3% on 4350B. A bare coupon therefore reads high by one to three percent, systematically, on every lot.

The fix is procedural: either measure after final cure on the finished article, or apply the mask offset as a known correction and state it on the certificate. What must not happen is a specification written for the masked product and a measurement taken on the bare coupon, because the error is one-directional and looks like a process drift.

An impedance certificate that reports a single value proves that one coupon on one panel was inside tolerance. A lot decision needs a distribution.

Five coupons is enough to see a 3% spread and not enough to prove a 1% shift. The point is not statistical rigour for its own sake — it is that impedance errors on a high-frequency build are systematic rather than random, so a small sample taken in the right places tracks the process far better than a large sample taken in one place.

The corrective ladder runs from the cheapest adjustment to the most expensive, and shops that start at the bottom spend a lot of money learning nothing.

The rule behind the table is that impedance is a product of two knobs that live in different departments — height in the press, width in the etcher — and a single measurement cannot tell you which one moved. Measuring both, on the same panel, is what makes the corrective action a decision instead of an experiment.

Impedance control is a loop with five joints: target, stack, coupon, measurement and corrective action. Designs fail at the joints, not in the equation — a coupon that does not represent the product, an instrument whose rise time cannot see the feature, a measurement taken before the mask, and a corrective action applied to the wrong knob.

The claims worth discarding are that a single coupon value certifies a lot (it certifies one point), that a 50 Ω reading is a property of the trace (it is an average over the rise time window), and that a bare coupon reading transfers to a masked product (it reads high by one to three percent, systematically).

XCE PCB measures impedance with TDR on product-panel coupons, at an agreed rise time with the launch de-embedded, five coupons per lot after final cure, against ±10%: 2–72 layers, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours. Where those numbers come from is set out in the stack-up design guide.