Testing in High-Frequency PCB Production: What to Measure, and Where

A generic test plan — visual inspection, electrical test, records, training — applies to any PCB. A high-frequency board adds two numbers that generic plans never touch: characteristic impedance and insertion loss. Neither is measured the way people expect, because the features that carry them are either buried or defined by geometry the bare board does not show. This article lays out the testing ladder from AOI to VNA, states what each instrument can and cannot prove, and gives the coupon rules that make the measurements worth signing.

Testing on a high-frequency build is a sequence of decreasing population and increasing information, and confusing the rungs is the most common source of false confidence:

The ladder matters because the two RF-critical numbers sit on different rungs. Impedance is verified per batch on coupons; loss is verified by sample. A board that passes flying-probe testing with 100% yield can still be out of specification at 28 GHz — the two rungs measure different physics.

Characteristic impedance cannot be read off a finished product line directly at production speed; it is measured by time-domain reflectometry on a coupon — and the coupon is only meaningful if it was built with the product. Five rules make a coupon trustworthy:

• Same geometry, same reference. The coupon trace must match the product line’s width, copper weight and reference spacing — a 20 mm wide coupon trace answers nothing about a 0.15 mm product line.
• Same lamination cycle. The coupon rides in the product panel through pressing, so the dielectric height it reports is the height the product actually got.
• Long enough. At least 50 mm of uniform line, so the TDR plateau is readable above launch artifacts.
• Enough coupons. Five per batch, tracked as a distribution — a single passing coupon says nothing about Cpk.
• Statistical control. Target Cpk ≥ 1.33 against the specified window; a mean sitting 4 Ω high with ±3 Ω spread is a process drift, not a pass.

When a coupon fails, the first diagnostic question is what moved: dielectric height (a lamination issue) or trace width (an etch issue). A 50 Ω line reading 53 Ω with correct width is a pressing problem; the same reading with a wide, thin trace is an etch problem. The closed loop is described in the impedance-control guide.

TDR resolution is set by the launch rise time: the smallest separable feature is roughly v · t_r / 2, where v is the propagation speed in the dielectric. On RO4350B, v is about 177 mm/ns:

Two consequences. A fast TDR can locate a defect to within a few millimetres along the coupon, which turns a failure into an attribution: the reading steps down at the transition into the press region (height problem) or along the etched length (width problem). And a slow TDR silently averages over defects — a line with a localised 15% impedance dip can still report a healthy average. Resolution is part of the test plan, not an instrument detail.

Laminate datasheets publish dielectric loss, but the board loses through the whole structure — dielectric, copper roughness, plating, finish and mask. The only number that closes a link budget is measured insertion loss on the finished structure, by VNA:

• Method. A coupon or qualification board with launched RF structures, measured S21 across the band, fixture de-embedded. Compare against the modelled budget — dielectric term plus conductor term plus the finish’s contribution.
• The finish is inside the measurement. At 10 GHz the skin depth in copper is 0.65 µm and the current in an ENIG trace flows in 3–6 µm of nickel, at twice the surface resistance of copper. On a low-loss laminate that can add 30–50% to insertion loss — which is why two boards of the same laminate with different finishes are not comparable, as covered in the surface-treatment guide.
• Sample basis, agreed in advance. Loss testing is destructive or fixture-bound; state in the drawing whether loss is verified per qualification lot or per batch, and on which structures.

A useful discipline: measure the coupon first bare-dielectric structures, then the finished product structures. The difference is the finish-and-mask penalty, measured on your own stack rather than assumed from an app note. The full measurement logic appears in the VNA verification guide.

Testing at the laminate stage is cheaper than testing at the assembly stage. Resonant methods (SPDR, split-post dielectric resonator) measure Dk and Df of incoming laminate lots in minutes, without building anything:

On PTFE builds the material check matters more than usual: sodium-naphthalene or plasma surface activation is invisible once copper is plated over it, and the first place a skipped or exhausted treatment shows up is a peel test weeks later — or a field return.

Generic environmental testing (high temperature, humidity, salt spray) applies to finishes and housings. For the RF structure itself, the discriminating tests are thermal, and they discriminate by material:

• Thermal cycling is the Z-axis test. Strain in the plated barrel is (Z-CTE − 17) × ΔT. Across −55 to +125 °C that is about 4.4% for RT/duroid 5880, 4.0% for TLY-5, 0.66% for FR-4, 0.30% for RO4350B — against a copper ductility of roughly 10%. High-Z-CTE PTFE boards pass, but with thin margins that only show up as cycling counts.
• Reflow simulation for mixed builds. Hybrid laminations join materials with different expansion; two to three reflow peaks find delamination far faster than months of shelf storage.
• Moisture exposure then reflow. PTFE absorbs almost nothing (0.02%), but FR-4 in a hybrid stack wicks water; a damp hybrid board reflowed without bake is the classic delamination source.
• Humidity bias for the finish, not the dielectric. Silver tarnish and tin whisker growth are humidity-driven finish problems, caught by biased humidity testing of the surface, not of the laminate.

The point of the list is proportionality: on a 5880 multilayer, hours of chamber time belong to thermal cycling of the barrels; on a 4350B four-layer, the reflow simulation is nearly a formality and the budget belongs elsewhere.

The output of testing is not a report; it is an attribution. Three practices separate a shop that improves from one that records:

• Split every impedance reading by cause. Height (lamination) or width (etch). The fix for the two is in different departments, and a report that averages them fixes neither.
• Trend coupons, not just gates. A Cpk drifting from 1.6 to 1.35 across ten batches is a warning with weeks of margin; a single out-of-window coupon is already an event.
• Feed loss measurements back to the model. Measured S21 above the budget by 0.1 dB/in usually means the finish or roughness term was under-modelled — which updates the next design, not just this batch.

Calibration and environment remain what they are in any lab: instruments on documented calibration cycles, coupons measured at room temperature against a temperature-stable reference. On PTFE laminates the dimensional sensitivity of the coupon itself to temperature is small, but the TDR launch fixture is not — warm fixtures read high.

Testing in high-frequency production is two measurement campaigns running alongside conventional QC: impedance, verified per batch by coupon TDR in the product’s own lamination cycle, and loss, verified by VNA on the finished structures. Everything else — AOI, flying probe, peel, solderability — guards the preconditions. A test plan that states which rung answers which question, with rise times and coupon rules written down, converts testing from paperwork into the process-control instrument it should be.

XCE PCB ships high-frequency builds with coupon TDR data per batch and VNA loss verification on qualification structures: 2–72 layers, impedance ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours.