Performance and Functions of HDI PCB: What Microvias Actually Buy, in Numbers

HDI is usually described as “smaller holes and more layers”, which is true and useless, because it does not say when the extra process is worth its cost. The definition that does work is mechanical: a microvia is 150 µm or less in diameter with an aspect ratio of at most 1:1, and that single constraint sets everything else — how thin a dielectric can be, which component pitch can escape, how many lamination cycles the build needs, and therefore what the board costs. This article works from that constraint: the escape arithmetic that decides whether HDI is required, the four performance claims that circulate most often and how much of each survives quantification, and the cases where a conventional through-hole build is the better engineering answer.

IPC-2226 defines a microvia by geometry: a laser-drilled via of 150 µm or less in finished diameter, spanning a single dielectric layer, with an aspect ratio of at most 1:1 — and 0.75:1 is what most fabricators prefer for plating uniformity. Everything that makes HDI expensive follows from that ratio, because the dielectric it crosses cannot be thicker than the hole is wide.

The build is described as M+N+M: M build-up layers on each side of an N-layer core. Each build-up pair adds a lamination cycle, and each cycle adds registration error, press time and scrap risk.

Two numbers in that table are routinely misquoted, and both matter commercially. The first is that the aspect ratio limit is not a manufacturing preference but a plating limit: at 1:1 the electrolyte has to exchange inside a blind hole with no through-flow, and beyond that the barrels void at the bottom. The second is that the dielectric thickness, not the hole diameter, is usually the free variable — a 0.1 mm microvia forces a 0.1 mm or thinner build-up dielectric, which in turn forces the impedance design to use narrow traces rather than thick dielectric to reach 50 Ω.

Whether a board needs HDI is decided at the first BGA, by how many traces can leave the ball grid on the same layer. Take the pad diameter, subtract it from the pitch to get the channel between adjacent pads, and see what fits: one trace with two clearances, or nothing.

The table explains why 0.65 mm is the practical boundary. At 0.65 mm a 0.1 mm trace passes with 0.1 mm on each side, which most fabricators hold comfortably; at 0.5 mm the geometry only closes with 0.075 mm lines and 0.06 mm gaps, so the board is now buying fine-line capability as well as microvias; at 0.4 mm there is no room for any trace between pads, and the escape has to happen through the pad itself, which means via-in-pad with copper fill and planarisation before assembly.

This is why the useful question is not “is this board HDI?” but “what is my largest BGA pitch, and does the fan-out close on the layer count I can afford?” A board with a 0.8 mm BGA and no other constraint does not need HDI at all, and adding it raises cost by roughly 30–40 % for a 1+N+1 build without changing anything the product can measure.

Partly true, and the part that is true is not the part usually quoted. A microvia fan-out shortens a net by a few millimetres at most compared with a through-via escape; at 5.45 ps/mm on Dk 3.38, three millimetres is 16 ps, which matters in a parallel bus with a 100 ps window and is irrelevant in a serial lane. Length is not where the electrical benefit lives.

The benefit is the stub. A through via in a 1.6 mm board leaves a stub below the layer where the signal enters, and that stub is an open-circuited transmission line that resonates at f = c/(4L√ε_eff). For a 1.6 mm stub in FR-4 that is about 23 GHz; in a 2.4 mm backplane it drops to 15.6 GHz. A blind microvia 0.08 mm deep puts the first resonance above 400 GHz, which is to say outside any band the product will use.

So the honest statement of the claim is: HDI improves signal integrity by removing the stub, not by removing the length. A designer who uses microvias but keeps long through-vias for the actual layer transitions has bought the cost and none of the benefit, which happens more often than it should.

This one reverses in practice. Crosstalk couples through the field between adjacent conductors, and the field strength for a given voltage rises as the dielectric gets thinner and the traces get closer. A 60 µm build-up dielectric with 75 µm traces at 75 µm spacing couples more tightly than a 200 µm core with 150 µm traces at 200 µm spacing — not less.

What HDI actually provides is the room to fix it. Dense microvia arrays allow ground vias between signal vias, and via-in-pad escapes free the channels that would otherwise be occupied by fan-out traces, so a differential pair can be routed with a continuous reference. The benefit is available, not automatic: near-end crosstalk in a 60 µm dielectric with no ground vias between differential pairs typically measures two to three times the value in a 200 µm dielectric with the same edge rate.

The design rules that make the claim true are unglamorous: one ground via per signal via at pitches below 0.5 mm, no pair routed without a reference plane on the adjacent layer, and no microvia field traversed by a single-ended signal without a return via within 0.5 mm. Written into the stack-up, they are worth 6–10 dB; left out, the dense build is worse than the conventional one.

The material does not do it. Build-up dielectrics are filled epoxies with thermal conductivity around 0.2–0.3 W/m·K — the same order as FR-4 and an order below any aluminium or ceramic substrate. What moves heat in an HDI board is copper, and specifically the via array under the thermal pad.

The arithmetic is worth doing once. A copper-filled 0.1 mm microvia through 0.9 mm of build-up and core has a thermal resistance of about 287 K/W; a 0.2 mm via is about 72 K/W. The same cross-section of laminate, at 0.3 W/m·K, is roughly 1,300 times worse. This is why a thermal pad with 20–30 filled vias behaves like a metal post and a thermal pad with two vias does not, and why the via count, fill and planarisation belong in the fabrication notes rather than in the mechanical drawing.

There is a real penalty on the other side: HDI boards are thin, and thin boards spread heat poorly in-plane. A 0.6 mm board has about 5 % of the bending stiffness of a 1.6 mm board of the same construction, and roughly a third of the copper cross-section available for lateral spreading. Heat leaves through vias and the opposite side, not through the plane.

Stiffness scales with the cube of thickness, so a thin HDI board is not stronger than a thick conventional one; it is much weaker. Against a 1.6 mm board, 1.0 mm retains 24 % of the bending stiffness, 0.8 mm retains 12.5 %, and 0.6 mm retains 5 %. What HDI changes is that the board is expected to be mounted on a frame or stiffener, or to be a rigid-flex with the flex portion doing the bending.

The mechanical requirements that do belong in a purchase order are different from “high-strength material”: warpage after each lamination cycle (typically held to 0.2–0.3 % of diagonal), registration between build-up layers (±25 µm for stacked microvias), copper fill flatness on via-in-pad (typically within 25 µm of the pad surface after planarisation), and microvia reliability by thermal cycling or IST. Those are measurable, and they are what actually fails in the field.

With the claims quantified, the applications sort themselves by which function they need rather than by industry name.

The last row is the one that concerns this site most, and it carries a constraint that is rarely stated. On a 0.254 mm microwave laminate, a 1:1 aspect ratio would require a 254 µm hole — which is not a microvia at all, and laser drilling of PTFE brings its own problems: the material does not absorb the CO₂ wavelength well, the debris is difficult to remove, and the Z-axis expansion of 237 ppm/°C loads the barrel far more than FR-4 does. Practical RF HDI therefore uses a thin build-up dielectric on the outer layers over a PTFE or mixed core, with the microwave routing kept on the core layers where the dielectric thickness is set by impedance, not by via geometry. The fabrication consequences of that split are in HDI production considerations.

HDI is priced by lamination cycles and yield, not by hole count. Indicative multipliers against a conventional multilayer of the same size, from fabricator quotations rather than list prices:

The break-even is easy to get wrong because the comparison is made per square metre instead of per product. Removing two layers from a 10-layer board saves the lamination, the copper and the drilling of those layers, and it typically shortens the route by 10–15 %; against that, HDI adds two laser drilling operations, two lamination cycles and a fine-line etch. On a 60×60 mm module the net difference is often within 10 %, which is why the decision should be made on yield and pitch, not on the price per panel.

There are four situations in which HDI is the wrong choice, and each has a physical reason rather than a commercial one.

Largest pitch 0.8 mm and above, with no area constraint. A through-via fan-out closes the design, the stub resonance at 23 GHz is outside the band for most products, and the 30–40 % premium buys nothing measurable.

High current. Microvias are 0.1 mm of copper after plating; a 0.1 mm finished microvia carries a few hundred milliamps comfortably and a couple of amps only with filled and capped construction. Power paths belong on the core layers with heavy copper, and the HDI layers route signals.

Thick microwave laminates. As above, a 0.254 mm dielectric cannot support a 1:1 microvia within the 150 µm definition, and PTFE laser drilling is a different process from FR-4 laser drilling. If the RF section needs 0.254 mm PTFE, that section stays conventional or uses blind mechanical vias, and the HDI build-up goes on the digital side of a hybrid stack.

Low volume. Tooling, laser program, lamination qualification and yield learning are fixed costs; at a few hundred boards a year, a 10-layer conventional build with a 0.65 mm fan-out is usually cheaper end to end even when the unit price per panel is higher.

HDI is a density technology whose electrical benefit is a by-product of geometry. The definition is a microvia of 150 µm or less at an aspect ratio of 1:1 or better, and that ratio forces the build-up dielectric to be as thin as the hole is wide — which gives fine lines, via-in-pad escape, and stub-free layer transitions, at the cost of one lamination cycle per build-up pair, tighter registration, and a board thin enough to need mechanical support.

The four claims that surround the technology should be read with their mechanisms: signal integrity improves because the stub disappears, not because the route is shorter; crosstalk gets worse unless ground vias and reference planes are added deliberately; heat moves through filled via arrays rather than through the dielectric; and stiffness falls with the cube of thickness, so the mechanical answer is a frame, not a stronger laminate. Get those four right and the decision becomes an arithmetic exercise at the first BGA.

XCE PCB builds HDI and mixed-dielectric boards against those constraints: 2 to 72 layers, microvia build-ups on FR-4 and on hybrid PTFE cores, impedance ±10 %, panels to 600×1200 mm, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. Send the largest BGA pitch and the stack-up you have in mind, and we will tell you which build closes it — and which one is more than the design needs. The process side is covered in HDI production considerations, and the definition and terminology in the HDI introduction.