Post-Processing in High-Frequency PCB Production: From Last Wet Step to Shipment

Post-processing is everything that happens to a board after its last wet process and before it is packed: final machining, cleaning, drying, inspection, marking and packaging. On a high-frequency build this stretch of the line does not change impedance — that was set in lamination and etch — but it decides whether the board arrives solderable, contamination-free and dimensionally true. It is also where a few standard assumptions quietly fail on RF laminates, starting with what cleaning is actually for.

Every build passes through some version of this chain; the order matters because each step protects the next:

Final machining sits first because the router finishes what design started: on PTFE builds, where the material creeps under lamination pressure, the milled outline is the first time the board is at its true final size — a fact the cutting guide follows from the other end of the process.

The usual justification — “a smooth surface helps signal transmission” — gets the threat wrong. A fingerprint does not measurably change insertion loss on a production line. What residues actually do is worse and slower:

• Ionic contamination migrates under bias. Leftover plating salts or activators combined with humidity form an electrolyte film; under voltage they drive electrochemical migration and dendritic growth between conductors — a latency failure that appears months into the field.
• Residues under the mask stay there. Organic films trapped before solder-mask application cause adhesion loss, chemically, on demand: ionic cleanliness is verified by ROSE testing or ion chromatography against the cleanliness spec of the assembly, typically expressed in µg/cm² of NaCl equivalence.
• Finishes are chemically sensitive. Immersion silver tarnishes from sulphur-bearing residues; ENIG gold bath contamination starts at the nickel surface and ends as black pad. Cleaning chemistry must be chosen against the finish, not just the flux.

Ultrasonic and spray-in-air aqueous cleaning are both standard; the watch item on RF builds is the same as everywhere else — aggressive chemistries attack exposed copper at antenna regions and test points where the finish is deliberately absent.

A bake before packing or assembly removes absorbed moisture so it cannot flash to steam in a reflow peak. The correct schedule depends on the material, and treating all laminates alike wastes time or risks damage:

Hybrid boards deserve the caution in both directions: the PTFE layers will not hold water, but the FR-4 core will, and a damp hybrid reflowed unbaked is the classic delamination source. Moisture that does no harm at packing still matters at the customer’s first reflow — which is why the packaging step, below, continues the drying job.

Routing and scoring at the end of the line carry the material rules of the cutting stage:

• PTFE machines, it does not saw. Sharp carbide tooling, high rake, low feed; the tool is changed by metres cut, because a dull tool smears the polymer surface instead of cutting it — and smear is the edge version of the hole-wall problem.
• Finished dimension is the milled dimension. PTFE creeps under lamination pressure, so the panel that went into the press is not the size that comes out; the outline, and any critical-to-function cutout, is verified after routing.
• Burr limits are functional, not cosmetic. Burrs along a scored edge interfere with pallets and fixtures; copper burrs inside holes plough solder paste and compromise barrel coverage. The same ≤0.05 mm edge-burr rule from fabrication applies here.
• No coolant where water would matter. On PTFE and hybrids, dry routing with vacuum extraction — water is a lamination-interface contaminant and the edge is the last place it belongs.

The last inspection gates three things at once: the physical board, the process data trail, and the electrical evidence from the batch:

• Visual and dimensional. Mask registration over antenna regions, finish uniformity on pads, outline dimensions, hole gauges, warp and twist against the thickness spec.
• Documentation. Lot traceability from laminate batch through press cycle to finish bath; the certificate of conformance states the impedance class and the coupon result.
• Electrical evidence. Coupon TDR data per batch, in the product’s own lamination cycle, against the specified window; VNA loss reports where the drawing asks for them — the measurement logic is in the testing guide.

One inspection habit pays for itself on RF builds: check the mask openings and antenna keep-outs against the fab drawing, not against habit. A solder-mask window opened where the design wanted bare PTFE changes the impedance of that region and is invisible in any electrical test short of a VNA.

Marking is a layout constraint, not a decoration decision. Three rules:

• Keep legend off RF structures. Silkscreen ink is a dielectric layer with Dk around 6.5; legend over a thin microstrip shifts its impedance exactly as the silk-screen guide quantifies — the same physics as solder mask, at smaller coverage.
• Laser marking where density demands it. Laser text avoids ink entirely but must stay off exposed finish and antenna regions; on PTFE the same thermal limits as cutting apply.
• Mark what traceability needs, and no more. Part number, revision, lot or date code; anything more crowds the board and risks the first rule.

Each finish ages differently, and packaging is chosen against the finish, not the board:

Vacuum packing with a humidity indicator card is the default for everything; on hybrid and FR-4 builds it also continues the bake’s work by keeping ambient moisture out of the laminate until the customer’s bake-out. A moisture barrier bag that has been opened and resealed has lost most of its value — date the seal.

Controlled environment helps: 22–25 °C and 30–50% relative humidity stabilise both the laminate and the measurement equipment, and dust control matters because particles on a panel before lamination become inclusions forever.

One standard claim needs correcting: bare high-frequency boards are not especially vulnerable to ESD. There are no devices to damage; the real post-processing hazards from handling are contamination and edge damage. ESD discipline — wrist straps, grounded surfaces, ionised air — becomes critical the moment components are mounted, and on RF assemblies it matters no more and no less than on any electronics line. Keeping the two stages distinct prevents spending protection effort in the wrong place.

Post-processing cannot rescue a board whose impedance or loss is wrong, and it does not need to: its job is to deliver the finished board with its properties intact — clean enough that ionic contamination never migrates, dry enough to survive the first reflow, machined to its true final size, and packaged so the finish the customer solders is the finish that left the line.

XCE PCB runs final machining, cleanliness verification, bake-by-material and finish-specific packaging on Rogers, Taconic and F4B builds: 2–72 layers, impedance ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours.