The Impact of Artificial Intelligence Development on the High-Frequency PCB Industry

Almost every article on this subject makes the same substitution. It sets out to describe how artificial intelligence is changing the circuit board industry, and ends up describing how circuit board factories use artificial intelligence — machine vision on the AOI line, predictive maintenance, a digital twin of the press. Those are real, but they are the smaller half of the story, and they are the half that is easiest to write without numbers. The larger half is that AI hardware has changed what a board has to be: more layers, more back-drilling, a different material mix and a yield arithmetic that turns a one percent process difference into a forty percent output difference. This article takes the two directions separately, because they have different economics and different bottlenecks.

The first causality runs from AI to the board: a training cluster needs accelerators, switches and optical links, and those products impose layer counts, materials and process steps that a general-purpose server does not. This is a demand-side impact, and it shows up as a change in the mix of work a fabricator receives rather than in the way the factory operates.

The second runs from AI to the factory: algorithms inspect images, classify defects, tune drill parameters and schedule presses. This is a supply-side impact, and it shows up as a change in cost per panel rather than in the product.

The two are usually written as one, which is why so much of the commentary is unfalsifiable. A demand-side claim can be checked against a stack-up and a yield figure; a supply-side claim can be checked against a defect escape rate. Separating them makes both testable, and it also explains an asymmetry that matters to anyone buying boards: the demand-side change has already happened and is visible in quotations, while the supply-side change is real but narrower than the vendor brochures suggest.

The demand-side change is easiest to see as a table, because the products are well defined even when the customers are not. Four board types account for most of the high-value demand, and they differ in layer count, material and the process step that becomes the bottleneck.

Two of those columns are worth dwelling on. Layer count in the twenties and thirties means twenty or thirty press-related opportunities to lose registration, and it means a finished thickness where the aspect ratio, not the drill diameter, sets the minimum hole. And low-profile copper appears in three of the four rows, which is a demand signal that reaches the foil supplier rather than the laminate supplier — a point that material comparisons usually miss, and that is quantified in PCB copper foils.

The fourth column is where the industry’s capacity is actually constrained. Back-drilling and build-up lamination are both serial operations with one machine per step, so a shift in demand toward AI boards does not simply load the drill floor; it loads specific machines that cannot be substituted by running faster.

The most under-appreciated consequence of the demand shift is arithmetic rather than electrical. A twenty-layer board is not one board; it is twenty chances to scrap it, and the compounding is brutal at the layer counts AI hardware uses.

Read across the 40-layer row: a plant that holds 98 % per layer ships 45 % of what it starts, and a plant at 99 % ships 67 %. The difference between those two plants is not a technology gap; it is a discipline gap worth roughly half the factory’s output on the same equipment and the same material. This is the real reason high-layer-count work concentrates among a small number of fabricators, and the reason a low price on a 32-layer quote is usually a signal that the yield assumption is optimistic.

The arithmetic also explains why scrap analysis pays better on AI boards than on consumer boards. On an 8-layer board, moving from 98 % to 99 % per layer gains seven points of output; on a 40-layer board it gains twenty-two. The defect Pareto that determines which of the two you achieve is dominated by a small number of causes — registration, lamination voids, plating thickness and drill smear — which is what a scrap programme should be pointed at rather than at the individual operator.

Five years ago back-drilling was a premium option quoted separately. On a board carrying 112G lanes it is structural, because a through-via that is only needed on the top few layers leaves a stub that resonates below the signal’s Nyquist frequency. A 1.6 mm residual stub resonates near 23 GHz on an FR-4-class stack, which is under the 28 GHz Nyquist of a 112G lane; back-drilling to a 0.35 mm remainder pushes the first resonance past 100 GHz.

The industrial consequence is larger than the electrical one. Back-drilling is a second drilling operation on the same hole, with a depth tolerance that has to be held against a reference layer, followed by its own inspection. That doubles the machine time on the drill floor for the affected holes, adds a depth-measurement step, and creates a new failure mode — a drill that stops short leaves too much stub, and one that goes deep damages the target plane. A factory that has not built the depth-control loop cannot quote AI boards competitively no matter how good its laminate stock is.

The design response is to reduce the number of holes that need it. Keeping high-speed signals on layers adjacent to the connector side, and using blind or buried vias in an HDI build, both shorten the stub without a second operation. That is one of the reasons HDI capability and AI board capability overlap so heavily — the structures are reviewed in HDI performance and functions.

A common assumption is that AI hardware has pushed the industry toward PTFE. It has not. It has pushed the industry toward controlled low loss, which is a different and much wider requirement, and the material mix that satisfies it is mostly hydrocarbon rather than PTFE.

The third row is the commercially important one. Hybrid stacks — low-loss material only under the high-speed layers, FR-4 elsewhere — are how AI boards are actually built, and they are why mixed lamination capability has become a qualification criterion rather than a nicety. They are also why a quotation that specifies a low-loss laminate full-board should be questioned: it is either a simple board or an expensive one. The comparison that most of these decisions come down to is set out in 4350B against 4003C.

Now the second causality, with the same discipline: each application is stated with what it can deliver and what limits it. The pattern is consistent — the algorithms are good at classification and parameter search on data the factory already generates, and weak wherever the ground truth requires a destructive test.

The first row is where most of the visible benefit sits, and it is a labour-substitution gain rather than a quality gain: the AOI machine already finds the defects, and the algorithm reduces the number of times a person has to look at a false call. That is valuable, and it is not the same as improving the process.

Four limits are worth stating plainly, because each one corresponds to a promise that gets made in sales meetings.

It cannot measure impedance instead of a coupon. The impedance of a production line is established by a physical coupon measured by TDR or VNA, and the reason is that the quantity depends on dielectric thickness and etched width, neither of which any algorithm can infer from an image. A model can predict where a line will land; only a coupon proves where it landed.

It cannot see inside a plated barrel. Barrel thickness, voiding and resin recession require a cross-section, which is destructive and samples a few points. Machine vision inspects what is on the surface; the reliability question is below it.

It cannot change the material. A dielectric constant is a property of the laminate, and no amount of process optimisation moves a 0.0037 dissipation factor to 0.0027. Where the channel budget does not close, the answer is a different stack — which is why the material discussion in high-frequency against standard PCB still precedes any software discussion.

It cannot help a factory with no data. Every application in the previous table trains on history. A plant that has not recorded drill parameters per laminate, press curves per stack and defect codes per station has nothing to train on, and the first task is instrumentation rather than intelligence. This, rather than cost, is why the adoption gap between large and small fabricators is widening.

Put the two causalities together and the cost structure of a high-value board changes in a way that a purchasing team can recognise from quotations. The table gives typical shares for a 20-layer high-speed board against a commodity 4-layer board, as ranges rather than point values because they depend heavily on layer mix.

The last row is the one that determines whether a quotation is credible. On a 24-layer board a ten-point difference in per-layer yield changes the effective cost by more than the difference between two adjacent laminate grades. A buyer who negotiates the laminate price and ignores the yield assumption is negotiating the smaller number.

AI demand has changed the supply chain in one specific way that affects design rather than price: the low-loss grades and the low-profile foils have longer lead times than the commodity laminates, and the second-source question is harder than it looks.

Substituting a laminate is not a drop-in change. A grade with a different Dk changes the trace width for the same impedance, which means a new artwork; a grade with a different Z-axis CTE changes the aspect-ratio and plating margins; and a grade with a different flame rating can change the compliance position of the whole product, since some hydrocarbon laminates carry a V-0 rating and some carry none. Two materials that look equivalent in a Dk/Df table can therefore require a full re-qualification.

The practical response is to specify a primary and an electrically equivalent alternate at the design stage, with the artwork recomputed for both, rather than discovering the need during a shortage. Where the design uses a high-Dk grade, the tolerance and the bondply thickness have to be re-checked as well, because the same physical stack with a substituted film can move impedance by several ohms — the mechanism is covered in the manufacturing process overview.

Forecasting is cheap, so three claims only, each of which is a consequence of the arithmetic above rather than a market prediction.

Back-drilling becomes universal on high-speed boards. The stub resonance of a 1.6 mm via sits below the Nyquist frequency of a 112G lane, so any board carrying those lanes must control stub length. This is not a trend; it is a requirement that follows from a wavelength.

HDI and high-layer-count converge. The two answers to the same problem — more layers raises stub length, more build-up raises press count — are being combined in the same board, which is why warpage and registration, not loss, are becoming the limiting yields.

Long channels move to optics. At 56 GHz the material-limited reach of the best laminate is about 1.2 m and the practical reach about half of that. Beyond that distance, copper stops competing with fibre on cost per bit, so board work concentrates on the last few hundred millimetres rather than on the backplane.

The article compresses into five questions that can be asked of any fabricator quoting an AI board, and each one maps to a section above.

The five are deliberately process questions rather than technology questions, because the technology is available to everyone who can buy the same laminate. What differs is whether the plant can hold a drill depth, compound a yield and prove it on a coupon — and those answers are what a credible AI board quotation is made of.

AI has changed the high-frequency PCB industry twice, in two directions that are usually merged into one paragraph. On the demand side it raised layer counts, made back-drilling structural, moved the material mix toward controlled low loss rather than toward PTFE, and imported a yield arithmetic in which a single point of per-layer discipline is worth half a factory’s output at forty layers. On the supply side it produced real but bounded gains: fewer false calls at AOI, faster defect Pareto, better parameter search on new laminates, all of them dependent on data the factory already has to record.

The claims that do not survive the arithmetic are the ones worth naming. AI does not reduce the need for an impedance coupon, because the quantity is physical and destructive to verify. AI does not turn a 0.0037 laminate into a 0.0027 one, because the loss floor is a property of the material. And AI does not shift the industry to PTFE, because most AI boards need controlled loss on four layers out of twenty, and a hybrid stack delivers that at a fraction of the cost.

XCE PCB builds these boards on the process side of the argument: 2 to 72 layers, 600×1200 mm panels, back-drilling with a defined residual stub, low-loss material localised to the high-speed layers, impedance held to ±10 % on a coupon, inspection to IPC-A-600G and IPC-6015, and samples in as fast as 24 hours. The channel arithmetic behind the material choices is set out in ten critical parameters for high-frequency PCBs, and the industry-wide view of where these materials are used in Rogers materials across industries.