PCB Structural Layers: What Each Layer Does and How the Count Is Decided

“Structural layers” gets used for two different things: the physical layers you see in a cross-section — legend, solder mask, finish, copper, prepreg, core — and the number of copper layers the board is built with. The first decides how the board behaves electrically and mechanically; the second is usually decided backwards, from how many reference planes the design needs. This article separates the two and gives the numbers for each.

When a fabricator says “layer structure”, they mean the sequence of materials through the thickness: which copper, which dielectric, which mask, which finish, in what order and at what thickness. When a designer says “layer count”, they mean how many copper layers exist. The two are related but they answer different questions, and confusing them produces the two most common stack-up mistakes: specifying a layer count without a reference-plane plan, and specifying a material stack without knowing the finished thickness the impedance was calculated on.

The layer count is covered from section 4. First, the cross-section — because four of those physical layers are electrical, not cosmetic.

A conventional two-sided board, in the order a cross-section shows it:

Two entries in that table surprise people often enough to repeat: solder mask and legend are electrical layers. A 50 Ω microstrip under 20 µm of Dk 3.5–4.2 mask reads 1–3 Ω low, which is why impedance coupons are measured bare and the finished board is allowed to sit slightly below nominal. On an RF line, moving a white legend stroke off a filter or a matching section is a layout rule, not a cosmetic preference.

Both are the same dielectric family, but they arrive in different states and that difference is the whole reason lamination is a process step rather than a press. Core is fully cured (C-stage): the resin has already reacted, the thickness is stable, and it can be handled, drilled and imaged on its own. Prepreg is partially cured (B-stage): the resin still flows under heat and pressure, which is exactly what makes it useful — it fills the copper topography of the layer below and bonds to it.

The consequence is a number: the finished dielectric height between two copper layers is not the core thickness, it is core thickness plus the pressed thickness of the prepreg plies. A 0.254 mm core with one 0.1 mm ply usually finishes near 0.32–0.35 mm, not 0.354 mm, because the ply consolidates. If a 50 Ω line was calculated on 0.254 mm and the stack actually presents 0.34 mm, impedance lands in the high fifties. This is the single most common cause of a first-article impedance miss, and it is why the lamination stage is treated as the step that finalises impedance rather than merely bonding the board.

Prepreg also shrinks. Cure shrinkage of 0.02–0.05% sounds negligible until it is multiplied by panel size: across 600 mm that is 0.12–0.30 mm of movement, two to six times the ±0.05–0.075 mm registration budget between layers.

The usual mistake is counting signal layers first and adding a ground layer at the end. Do it the other way round: every signal layer needs an adjacent continuous reference plane, and the count follows from that rule.

• Microstrip (outer layer) needs one plane below it.
• Stripline (inner layer) needs a plane above and below — two planes per signal layer.
• Coplanar waveguide needs ground on the same layer as well as below, which costs routing width but allows a two-layer board to carry controlled impedance at all.

Therefore n stripline layers require n+1 planes. A four-layer board with two inner signal layers would need three planes and has only four layers total — which is why almost all four-layer boards use the two inner layers as planes and put signals on the outside, as microstrip. They have exactly two controlled-impedance layers, and no stripline at all. A two-layer board has none: it can only offer coplanar waveguide or a very wide microstrip over a fragmented ground pour.

For how the impedance geometry changes with layer position, the stack-up design guide covers the width tables; the point here is that the count is a topology decision made before any trace is routed.

Each step costs money non-linearly, because each added pair of layers is another lamination cycle and another registration opportunity. Four to six is a modest step; six to ten is not, and at that point the choice between more layers and HDI (finer lines, microvias) becomes a genuine trade. The four-layer and six-layer articles cover the process precautions specific to those two workhorses.

A through via occupies every layer it passes through, so it blocks routing on all of them. Blind vias (outer to inner) and buried vias (inner to inner) free the layers they do not touch, which is how HDI achieves density without adding layers. The trade is explicit: each blind or buried level requires an additional lamination cycle, and each cycle adds drilling, plating, registration and yield risk.

So the cost claim in most articles is backwards. Blind and buried vias do not reduce cost by reducing layer count; they increase cost per layer while allowing a lower layer count to reach a given density. Whether that nets out cheaper depends on volume and yield. On a small board with dense fan-out under a BGA, HDI usually wins. On a large board with moderate density, more layers usually wins. In RF terms there is one more consideration: a buried signal layer has a dielectric above and below, so it is a true stripline and its impedance is roughly 2.5 times more sensitive to etch variation than an outer microstrip of the same dielectric height.

Four things affect performance but never appear in “how many layers”: the mask, the legend, the finish, and any stiffener or thermal structure.

• Mask as an electrical layer: Dk 3.5–4.2, thickness 10–25 µm. On a 0.2 mm line it shifts impedance by several ohms; on a 0.56 mm line by one or two.
• Legend as an electrical layer: cured ink Dk around 6.5. It is a local dielectric perturbation; over a filter it is a tuning error.
• Finish as an electrical layer: nickel inside the skin depth above 10 GHz; see the finish discussion in the surface treatment guide for when that matters.
• Stiffener, thermal pad, cavity: mechanical or thermal structures that change the cross-section without changing the copper count.

Once the stack is settled, the next decision is which layers use which dielectric. The commercial pattern is high-frequency laminate on the outer layers and FR-4 in the centre, because the RF lines are usually on the outside and because keeping the core symmetric controls warp. The process consequence is that PTFE and FR-4 cannot be co-pressed in one cycle — the PTFE section is laminated as a sub-assembly at 260–300 °C, then bonded to the FR-4 at 190–200 °C. One material per board is simpler; two materials on a board with a defined boundary is routine; two materials interleaved through the stack is where yield goes.

Terminology for the whole cross-section — core, prepreg, B-stage, C-stage, barrel, annular ring — is collected in the PCB processing terminology article if a shared vocabulary would help the review.

The cross-section and the layer count are two decisions, taken in that order. First, what the dielectric stack is — core plus pressed prepreg, plus the mask and finish that also carry current — because that is what the impedance was calculated on. Then how many copper layers, derived from the reference-plane requirement rather than from the signal count. Everything else (blind vias, HDI, mixed materials) is a cost trade layered on top of those two.

XCE PCB builds 2–72 layer boards in FR-4 and the RF laminate range, with impedance held to ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, and samples in as fast as 24 hours.