PCB Photolithography and Etching: What Each Step Controls, and What It Cannot Fix

Two steps, often described as one. Photolithography defines an image in photoresist; etching transfers that image into copper and then keeps going, sideways, whether or not anyone wanted it to. The distinction matters because the defects look identical on the finished board — a line that is 15 µm narrow could come from under-exposure, over-development or over-etch — and because neither step can rescue a stack-up whose dielectric height or Dk was wrong to begin with.

Photolithography is an imaging process: coat or laminate a photosensitive resist, expose it through a film or with a laser, develop it. What remains is a stencil of cured polymer on copper. Etching is a removal process: put the panel in contact with a solution that dissolves copper, and let the resist decide where that happens.

The boundary is worth stating precisely because it determines who owns which defect:

The last row is the one that costs money. Etching moves line width by a few microns; the same few microns are worth about 0.6% of impedance per 1% of width. Dielectric height is worth roughly 0.6% per 1% of thickness. Both are real, but they are not the same size of lever, and no amount of etch control compensates for a pressed dielectric that came out 0.08 mm thick instead of 0.06 mm.

Five variables, and each has a visible consequence on the finished trace:

Two corrections to how this step is usually described. First, the resist does not protect “the unexposed area” in general — it protects whatever remains after development, which for a negative resist is the exposed area and for a positive resist is the unexposed area. Articles that name one direction as universal are describing half the chemistry. Second, faster exposure is a throughput variable, not a yield variable: dose sets line width and sidewall angle, and pushing it to raise throughput moves both.

Wet etching of copper is a chemical dissolution run at a controlled rate. Five parameters define the rate, and all five move during a production day:

Note what is not on that list: the target line width. Etching removes copper isotropically, so it cannot be told to remove 12 µm vertically and 3 µm laterally. That ratio is a property of the process — the etch factor, typically around 2.5 for spray etching — and the only way to control the lateral loss is to control the copper thickness and the time. The arithmetic (side etch equals copper thickness divided by etch factor) is worked through in the inner-layer fabrication article, because that is where it is usually applied.

An etch line can hold a nominal line width and still fail, because what matters is the distribution. Three effects stack up:

• Position on the panel. Etchant arrives at the leading edge fresh and at the trailing edge partly spent; nozzles cover the centre differently from the edges. A ±5–10% spread in etch depth across a 600 mm panel is normal, and it translates directly into a line-width spread.
• Copper loading. A panel with 70% copper coverage consumes the bath far faster locally than one with 30%. Mixed panels in the same load etch unevenly, which is why heavy-copper and light-copper work is usually batched separately.
• Feature density. Isolated lines etch faster than lines inside a dense array, because the local etchant is renewed more freely. This is the mechanism behind “same drawn width, different measured width” on one board.

The practical consequence for RF work: a coupon placed at the panel edge does not represent a filter in the centre. Coupons should be placed where the critical features are, and, if the design has both, one at each. The impedance consequences of a width error are quantified in the impedance control article.

• Dielectric height. Set by core thickness plus pressed prepreg. Etching cannot reach it.
• Dk and Df. Material properties. A line that measures perfectly and sits on the wrong laminate is still the wrong impedance.
• Layer registration. Set by the exposure tool and by lamination movement; etch only makes a misregistered pad smaller.
• Copper roughness. Foil property. At 10 GHz roughness dominates conductor loss on smooth-foil budgets, and no etch recipe changes it.
• Surface finish. A separate step entirely. Nickel thickness on an ENIG board matters more above 10 GHz than a 5 µm line-width error.

This is why a line-width measurement alone is a weak acceptance criterion. It confirms the etch step did what it was told; it does not confirm the board is the board that was designed. The measurement that does that is a coupon TDR or S-parameter result, in the same place on the panel as the critical features.

Dry etching — plasma or reactive ion — is anisotropic: it removes material vertically far faster than laterally, which is why semiconductor fabs use it. On a PCB it is not a patterning method, for two reasons. Copper has no volatile plasma product at practical temperatures, so the removal rate is unusably slow; and panels are large, thick and covered in resist that would not survive the process.

Plasma does have two real jobs in PCB fabrication, and both are often confused with etching: desmearing drilled holes, and activating PTFE surfaces before plating. Those are surface preparation, not pattern transfer. The full sequence of steps and where each sits is mapped in the manufacturing process guide.

• Drawn width versus finished width. Say which the Gerber represents, and state the compensation if any. A fabricator who assumes the other convention produces a board that is uniformly wrong.
• Copper thickness for the layer, because it sets the side etch: 0.5 oz, 1 oz and 2 oz lose roughly 7, 14 and 28 µm per side at an etch factor of 2.5.
• Imaging capability if the design has features below 0.075 mm: LDI, or film with a documented expansion allowance.
• Where coupons go, and whether one per panel or one per critical feature group.
• Line-width tolerance as a finished dimension, with the measurement method named — cross-section and AOI give different numbers.

Photolithography decides where copper will remain; etching decides how much of it survives, in both directions. Treating them as one step makes every width defect ambiguous, and ambiguity is expensive: it sends investigation to the etch bath when the problem was resist adhesion, or to the artwork when the problem was panel position. Separate the two, measure the resist before etch, and place coupons where the critical features are. Then accept the one thing wet etching will not do — a vertical wall — and design the copper thickness around it.

XCE PCB runs LDI imaging, cupric-chloride etching with per-panel coupon control, and PTFE-qualified plasma activation: 2–72 layers, impedance held to ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours.