Inner Layer Circuit Fabrication for High-Frequency PCB: Eight Steps and the Etch Budget Behind Every Trace

On the outer layers you can still trim a stub or swap a component value. On the inner layers the impedance is decided by a chemical bath, forty minutes before anyone measures it. That is why the etch step — not the exposure step — is the one that deserves the process window: exposure puts the pattern in the right place, etching decides how wide it ends up, and width is impedance. These are the eight steps, with the numbers that go wrong in each.

A controlled-impedance inner layer is the product of four numbers: the Dk of the dielectric, the pressed height of the gap, the copper thickness, and the finished trace width. The first two are fixed at the stack-up and lamination stages; the last two are decided here, in imaging and etching. Everything downstream — drilling, plating, routing, test — can only preserve or damage what this step produced.

That order matters when something comes back wrong. An inner-layer trace that reads 54 Ω instead of 50 Ω cannot be corrected by a better finish or a tighter AOI setting; the only remaining option is to scrap the panel and re-etch. The process window is cheap to hold and expensive to recover, which is the whole argument for treating etching as a controlled process rather than a tank with a conveyor over it.

This is step four in the twelve-step manufacturing sequence, following the cut and pinned panel described in the substrate cutting guide.

The panel arrives pinned to a datum, with the material recorded by lot. Before any resist goes on, the copper surface has to be clean, uniformly roughened and free of oxide — and on PTFE the usual mechanical cleaning is the wrong tool.

• No brush scrubbing on PTFE. A mechanical scrubber is standard practice on FR-4 and destructive on a soft fluoropolymer: it smears the surface, embeds debris and changes the copper-to-dielectric transition at the trace edge, which is exactly the region that carries the current at millimetre wave. Chemical cleaning and a controlled micro-etch instead.
• Micro-etch removes copper, so it moves the impedance. A 1 µm micro-etch on 35 µm copper is harmless; a bath running hot can take 3–5 µm, which on a 17 µm inner layer is a measurable change in thickness and therefore in conductor loss.
• Record thickness and lot per sheet. Sheet thickness varies lot to lot and Dk varies with it — the extreme case being 0.101 mm RO4350B, footnoted at Dk 3.36 against the 3.48 nominal. The lamination stage needs that number before it chooses the bondply.

The pattern is transferred by exposing a photoresist through a mask (contact printing) or by projecting it directly (laser direct imaging). Both work; they fail differently.

Contact printing depends on a polyester phototool that changes size with temperature and humidity. Over a 600 mm panel, a film that scales by 40 ppm — an ordinary number for PET across a shop’s humidity range — is 0.024 mm out at the far edge, and the error is not uniform across the panel. That is survivable for 0.15 mm lines and marginal for 0.075 mm ones. LDI writes the pattern from the CAD data with no film in the optical path, so registration is referenced to the panel’s own fiducials and the film-scaling term disappears.

Practical split: contact printing for 0.10 mm and above where the shop is stable and the film is young; LDI for anything at or below 0.075 mm, for high layer counts where accumulated registration matters, and for high-frequency inner layers where a 5 µm width error is a measurable impedance error. Exposure energy has to be matched to the resist and the copper topography — under-exposure leaves a resist foot that etches into a trapezoid, over-exposure closes fine gaps before the etcher ever sees them.

Inner-layer patterning is a wet process. The two chemistries in production are cupric chloride and alkaline ammonia; ferric chloride still appears in smaller shops and for special work. What is not used, at 17 to 70 µm of copper, is plasma or laser.

That deserves a direct statement because it is a common claim in generic descriptions: plasma etching of copper runs at roughly a micrometre per minute, which makes removing 35 µm a job of hours, and laser ablation of a full inner layer is not a production process at all. Both technologies have real roles in a high-frequency shop — plasma for desmear and for activating PTFE hole walls, laser for direct imaging and drilling — but neither removes the copper pattern. Nor is copper sulphate an etchant; it is the electrolyte in the plating line next door.

What the etcher has to hold is three variables: chemistry concentration, temperature (±1 °C matters), and conveyor speed. The output that matters is not “clean etch” but the etch factor — the ratio of vertical to lateral removal. An isotropic bath etches sideways as fast as it etches down, and the sideways component is what narrows the trace.

Lateral etch scales with copper thickness, so the same bath is a different process on 0.5 oz and on 2 oz. At an etch factor of 2.5, a 35 µm layer loses 14 µm per side while a 17 µm layer loses 7 µm.

Read the last two columns together and the rule appears. The same 14 µm of undercut is 2.5% of a 50 Ω line and 14% of a fine control line — so copper weight is a fine-line decision, not just a current-carrying one. In impedance terms, on 0.254 mm RO4350B: the 0.56 mm line moves from 50.0 to 50.8 Ω (+1.6%, tolerable), while a 0.10 mm line moves from 113 to 119 Ω (+5.3%). Push to 2 oz and that same narrow line loses 28% of its width and reads 126 Ω — the fine geometry stops existing as designed.

This is why high-density inner layers on high-frequency boards are built on 0.5 oz copper, and why the stack-up has to agree to it before the laminate is ordered. It is also why the etch factor is a process parameter worth measuring rather than assuming: an etch factor of 3 instead of 2.5 buys back 3 µm per side, which is the difference between 119 and 116 Ω on that narrow line.

Fabricators compensate for undercut by drawing the trace wider on the artwork than the finished dimension, typically by about one copper thickness total across the line. The compensation is routine and it works — as long as the number in the data package is unambiguous.

If the design file gives finished widths and the fabricator applies compensation, the result matches the model. If the design file gives artwork widths — which happens when a layout is copied between shops with different processes — the finished line is one copper thickness narrower than intended, and on a 0.10 mm line that is the 14% already tabulated. This is a documentation failure, not a process failure, and it is the same class of problem as quoting a design Dk where the fabricator builds to the process value: both are resolved by one sentence in the notes. The conventions are set out in the hybrid design file guide.

The second half of width control is the resist. For 0.075 mm features use a thin dry film or an LDI-matched liquid resist; a thick film cannot resolve the gap, and a resist foot left by under-exposure produces a trapezoidal cross-section that measures correctly on top and reads low in impedance.

After etching, the resist comes off in an alkaline stripper. Two things go wrong at this step, both of them quietly.

Resist residue. A partially stripped film leaves a film of polymer on the copper that is invisible under normal light and insulating under a bond ply. It survives lamination and shows up as a delamination site or a via with no connection. The check is a water-break test: a clean copper surface holds a continuous water film for 30 seconds; a contaminated one breaks into droplets.

Over-stripping. Aggressive stripping attacks the bond treatment that comes next, and on thin inner layers it also attacks the copper itself. The strip chemistry, concentration and temperature belong in the process sheet, not in the operator’s judgement.

Copper topography is the third, structural issue. At millimetre-wave frequencies the conductor loss depends on the foil profile — the roughness that helps adhesion also increases attenuation — which is why low-profile foils are specified on high-frequency inner layers. Nothing downstream can restore a rough foil, and no AOI can see it.

Automated optical inspection compares the etched pattern against the CAD image. It is genuinely good at opens, shorts, nicks, spacing violations, missing features and registration offsets — and it is routinely asked to prove things it cannot measure at all:

• Impedance. AOI measures geometry in two dimensions against a nominal image; it has no idea what the dielectric height is doing, and it does not convert width into impedance. That is the coupon’s job, by TDR.
• Etch factor and sidewall angle. A top-down camera sees the top width, not the cross-section. A trace that measures 0.100 mm on top and 0.072 mm at the base passes AOI and fails the model.
• Copper thickness and foil profile. Both need a cross-section or a dedicated measurement, not an image.
• Resist residue, oxide quality, bond readiness. Chemical states, invisible optically.

So AOI is a defect screen, not a process certificate. The width number that goes into the impedance calculation should come from a coupon measured after etch — a short test line etched in the same panel, measured optically or by cross-section — and the number should be recorded per lot. Two consecutive lots that both “pass AOI” can differ by 10 µm in finished width, which is 6% of impedance.

The last chemical step on the inner layer exists to make the copper bond to the prepreg. There are three routes and they are not interchangeable across materials.

The pink-ring mechanism is worth knowing because it appears months later as a field failure. Black oxide is a thick, porous copper oxide; if the prepreg carries moisture, the oxide dissolves at lamination temperature and leaves a pink halo around every hole where the copper was consumed. Thin oxide or an oxide alternative removes the reservoir. On PTFE the whole question is different: there is no oxide bonding chemistry for a fluoropolymer, so the surface is activated with sodium naphthalene or plasma and the bond is carried by an FEP film or a low-flow prepreg — the route described in the 5880 and FR-4 lamination guide and in the hybrid lamination analysis.

Three housekeeping items decide whether a correctly etched inner layer survives the press.

The registration figure is the one that binds everything else. On an eight-layer build, a ±0.075 mm layer-to-layer error consumes the whole annular ring at 0.05 mm clearance before the drill position tolerance is even applied, which is why high layer counts on high-frequency laminate get the tighter figure and the pinned, LDI-exposed route.

Inner-layer fabrication is not complicated; it is unforgiving. Image transfer fixes position, etching fixes width, and width is impedance — so the etch factor, the copper weight and the width convention in the data package are the three numbers that decide whether the layer you laminated is the layer you simulated. The two claims worth discarding are that inner layers are dry-etched (they are not; plasma belongs to desmear and PTFE activation) and that AOI certifies the pattern (it screens defects and sees no cross-section, no thickness and no impedance).

XCE PCB runs inner layers on Rogers, Taconic and F4B laminate with LDI imaging, measured etch factors and impedance coupons on every RF lot: 2–72 layers, impedance ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours. The stack that these widths are calculated against is set in the stack-up design guide.