Plating High-Frequency PCB: A Copper Barrel That Has to Stretch With the Laminate

Plating is usually described as making the hole conductive. That is the easy half. The hard half is mechanical: the copper barrel is a thin metal tube bonded to a dielectric that expands several times more than copper in the Z axis, and it has to survive every thermal cycle the product will ever see without cracking. On FR-4 that strain is a fraction of a percent. On unfilled PTFE it is over four percent — against a plated copper elongation of roughly ten. Everything else in this step, from seed thickness to current density, exists to keep that margin.

Plating does two things that are often discussed as one. Electrically it makes the barrel continuous, which is a coverage problem. Mechanically it makes the barrel a structural member, which is a ductility and thickness-distribution problem. A process tuned for the first will produce a barrel that passes continuity and cracks after two hundred cycles.

The split matters more on high-frequency laminate than on FR-4 for a reason that has nothing to do with the plating bath: the dielectric moves. Z-axis CTE for RT/duroid 5880 is 237 ppm/°C against 17 for copper, and the coefficient that matters for a barrel is the difference.

Two to three times margin sounds adequate until the concentrators are counted: the strain is not uniform along the barrel, the copper at the hole corner is thinner than the average, and the plating is only as ductile as its worst point. That is why a PTFE build is a plating specification, not just a drilling one.

Class 3 work is specified as an average barrel thickness of 25 µm with a 20 µm minimum, measured on a cross-section. The average is the number that gets quoted; the minimum is the number that fails.

The seed figure is worth stating plainly because it is widely misquoted. Electroless copper is a catalyst layer, not a conductor: it is 0.25–0.5 µm thick, deposited at roughly 2–3 µm per hour, so the step takes minutes rather than an hour. A process that deposits 1–2 µm has either run four times too long or is doing panel plating under a misleading name — and the extra thickness buys nothing, because the current-carrying copper is put there by the electrolytic step anyway.

On FR-4, preparation is cleaning: remove oxide, remove oil, leave a micro-etched copper surface. On PTFE the same procedure produces a chemically inert wall that copper will not bond to, no matter how clean it is.

The activated surface has to be created. Sodium naphthalene or plasma treatment removes fluorine from the polymer chain and leaves a carbon-rich layer with enough surface energy for the seed to anchor — the same treatment described in the drilling and desmear step. On a hybrid build the hole passes through both materials, so the two halves of the same barrel are prepared by different chemistries, and the transition zone is where pull-away starts.

Two checks belong here and are routinely skipped: a water-break test on the wall (a continuous film for 30 s), and a seed-coverage check by backlight, where a plated section is examined against a light source. A backlight rating below about 8–9 out of 10 means the seed is incomplete before the electrolytic tank ever sees the panel.

The seed layer has one job: make the wall conductive everywhere, so that the electrolytic step can start from a continuous electrode. Its failure mode is a void, and a void is not a thickness problem — it is a hole in a 0.3 µm film, which no downstream step will fill from the inside.

Where voids come from: air trapped in the barrel, a bubble clinging to the wall, drag-in contamination from the previous bath, insufficient agitation, or a wall too rough for a 0.3 µm film to follow. The countermeasures are mechanical rather than chemical — vibration or panel movement in the tank, air knives, and a wetting agent that actually wets a fluoropolymer.

Bath control is the other half: temperature around 45–50 °C, controlled loading in square decimetres per litre, and analysis by titration rather than by the calendar. A bath that is allowed to drift deposits a seed that is thinner at the hole centre than on the surface, and the difference shows up later as a barrel that plates thin exactly where the strain is highest.

The choice is usually made for capacity reasons and paid for in the etch step. Panel plating deposits copper over the whole surface before imaging; pattern plating images first and plates only into the pattern.

The consequence is quantitative, and it is the same arithmetic as the etch budget in the inner-layer guide: lateral etch scales with copper thickness. Adding 35 µm of panel copper to a 17 µm inner layer triples the undercut, and a 0.10 mm line loses 28% of its width instead of 7%. For high-frequency work with fine features, pattern plating is what keeps the width the model asked for.

On microstrip the surface copper thickness is itself an impedance term: going from 1 oz to 2 oz on a 0.254 mm build widens the effective conductor and drops impedance by roughly 2%. That is inside a ±10% window but not inside a ±5% one, so the stack-up and the plating spec have to agree on which copper weight the model used.

Current density is quoted in amps per square foot, typically 15–30 A/ft² (about 1.6–3.2 A/dm²) for panel and pattern plating of PCB work. Higher density plates faster and distributes worse; lower density plates slower and more uniformly.

Uniformity along the barrel is described by throwing power — the ratio of copper thickness at the hole centre to thickness on the surface. It falls as aspect ratio rises, because the electrolyte inside the hole is depleted faster than it can be replenished.

Read the last column and the real cost of a high aspect ratio appears. To hold 25 µm inside a 5:1 hole the surface has to carry 42 µm, which then has to be etched back — and at 8:1 or 10:1 the surface copper required starts to conflict with fine-line etching altogether. That is why the aspect-ratio limit on PTFE is set at about 6:1 in the drilling step: it is a plating limit expressed as a drilling rule.

Two process aids do most of the work at moderate aspect ratios: solution agitation at the panel face, and periodic current reversal or pulse plating, which replenishes the boundary layer inside the hole and narrows the distribution without raising the average thickness.

Elongation is the property that decides whether a 4.4% Z strain is survivable. Class 3 work generally calls for plated copper elongation around 10–12% measured on a test coupon, and that number is a function of the bath: too much organic brightener, too high a current density, or contamination all raise tensile strength and lower elongation.

A barrel that measures 25 µm and 8% elongation will pass every dimensional check and fail in a thermal shock test. The check that catches it is a coupon plated in the same load, pulled and measured — not a thickness measurement on a cross-section.

After plating, a bake at 120–150 °C for a few hours relieves hydrogen absorbed during the process and stabilises the deposit before the panel sees reflow. It is not a stress-relief anneal in the metallurgical sense, and it will not rescue a brittle deposit: it removes a known failure mechanism rather than improving the copper.

Thermal cycling failures in plated barrels are concentrated, not random. The three sites to look at on a cross-section after cycling:

• The knee, where the barrel meets the surface pad. The copper turns a corner, the deposit is thinnest, and the strain reverses direction. Most barrel cracks start here.
• Mid-barrel, over a bond ply. This is where the dielectric expansion is largest on a hybrid build, because the bond ply is the softest layer in the stack.
• The wall itself, where the seed did not cover. Not a fatigue failure but a void, and it opens on the first cycle rather than the hundredth.

The design answers are unglamorous and effective: thicker plating at the knee, a larger annular ring to spread the strain, a controlled aspect ratio, and back-drilled or blind structures that keep the barrel short. On 5880 the margin is 2.3×, so all four are usually applied together rather than chosen between.

Plating is the step that turns a hole into a component, and on high-frequency laminate the component is a fatigue part. The two numbers that decide it are not the ones usually quoted: not the average thickness, but the minimum at the knee, and not the current density, but the elongation the bath actually delivers.

The claims worth discarding are that electroless copper is 1–2 µm thick (it is 0.25–0.5, and thicker buys nothing), that a thicker deposit always improves reliability (it improves current capacity and worsens the etch budget), and that a standard clean prepares a PTFE wall (it has to be activated, or the barrel will pull away).

XCE PCB plates Rogers, Taconic and F4B builds with sodium naphthalene or plasma activation, backlight-verified seed, aspect ratios capped at 6:1 on PTFE and coupon elongation measured per load: 2–72 layers, impedance ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours. The finish that goes over this copper, and the imaging and routing steps around it, are mapped in the twelve-step manufacturing sequence.