Unlocking High-Frequency Circuit Design: The Layer Cake, Priced in Tolerances

The layer cake is the best metaphor in PCB engineering and the most misleading. It suggests that a stack is assembled from ingredients — core, foil, prepreg, mask — when in fact it is assembled from tolerances, and each layer contributes a specific number of ohms to the answer. A designer who thinks in ingredients chooses a 0.254 mm core for 50 Ω; a designer who thinks in tolerances discovers that the 0.10 mm of bondply above it was never counted, and that the same trace is really 61 Ω. This guide walks the five layers in the order the field sees them, gives each one its electrical job and its tolerance contribution, and ends with the arithmetic that turns a stack drawing into a measured impedance.

As a teaching device the layer cake is excellent: it separates the structural core, the copper that carries the signal, the adhesive that bonds, and the coating that protects. As a design device it fails at exactly the point where money is spent, because a cake is judged on its layers and a stack is judged on the thickness between two of them. Every electrical property of a high-frequency board — impedance, wavelength, loss per unit length, coupling — is a function of the dielectric height and the copper width, and the height is a sum of parts that are each toleranced separately.

So the useful version of the metaphor is this: five layers, five jobs, five tolerances, one result. The result is the number that appears on an impedance coupon, and if the five tolerances are not added up before the panel is released, that number is an accident rather than a specification.

The core is the only layer a designer usually chooses deliberately, and it fixes the trace width for a given impedance. On a Dk 3.38 laminate the 50 Ω microstrip solution is a ratio: W/h ≈ 2.33. The width therefore follows the core thickness whether the layout wants it or not.

The wavelength column is constant on purpose. Electrical length is set by Dk, not by thickness; a thicker core changes the width, the loss per inch and the coupling, but not the phase per millimetre. That is why a phase-sensitive design can move to a thicker core to cut copper loss without retuning the matching network — and why a design that changes Dk cannot.

Copper foil is specified by weight, and weight is a proxy for thickness: 1 oz means 35 µm of base copper. On an outer layer the trace is then plated up to 50–60 µm during pattern plating, so a drawing that says 1 oz and a drawing that says 50 µm finished are describing the same thing from two different ends of the process.

The property that matters at high frequency is profile. At 10 GHz the skin depth in copper is 0.65 µm; at 28 GHz it is 0.39 µm. Standard electrodeposited foil has a nodular treatment several micrometres tall, so the current follows a surface that is longer than the geometric width. Very-low-profile foil reduces that penalty. Reverse-treated foil does not: it puts the smooth side outward for imaging and the treated side into the bond, which is a fine-line benefit rather than a loss benefit. Choosing RTF in the belief that it lowers insertion loss is one of the quiet mistakes in high-frequency stacks.

For the loss arithmetic on copper, the specialised treatment is in copper thickness in high-frequency PCBs; here the point is only that the foil is a layer of the electrical stack and not a commodity.

Prepreg becomes bondply after pressing, and it contributes dielectric height that sits between the core and the reference plane. The dielectric height that governs impedance is therefore not the core thickness but the core plus the pressed bond thickness — and this is where the single largest avoidable error in stack design occurs.

Read the +22 % row against a ±10 % specification and the problem is obvious: one uncounted bondply is more than twice the entire tolerance window. It also cannot be recovered by etching the trace narrower, because the fix would require a width 30 % smaller, which the etch process and the current-carrying requirement may not allow. The only reliable fix is to count the bondply at design time and to state the pressed thickness, not the prepreg grade, on the drawing.

Bondply is also electrically different from the core. RF bondplies are commonly Dk 3.3–3.6, close enough to a 3.38 core to be ignored in the arithmetic but not in the loss; and its resin content determines how much it flows, which determines the pressed thickness. A supplier quoting “one ply of prepreg” without naming the grade has not specified the dielectric height.

Solder mask is not electrically neutral. It has a dielectric constant of roughly 3.5–4.2 for standard liquids and higher for some pigmented formulations, it sits directly on the trace, and it lowers impedance by a few ohms because it replaces air above the conductor with a dielectric.

The correction to the original explanation is that opening the mask does not let the signal travel “in pure air”. It restores an air interface locally, which raises the impedance slightly, and it introduces two transitions where the effective permittivity changes. It also exposes copper that must then be finished with something — OSP, ENIG, immersion silver — and that finish becomes the conductor. For a 28 GHz line, a mask opening with a nickel-containing finish is often worse than a thin mask left in place. The trade-offs between finishes are compared in PCB surface treatment processes.

A stack that is not mirrored about its centre line will bow after pressing, because the two halves shrink differently as the resin cures. The mechanism is straightforward: prepreg shrinks 0.02–0.05 % during cure, which on a 600 mm panel is 0.12–0.30 mm of movement, and if that movement is not balanced the panel relieves it by warping.

The rule is to mirror material type, thickness and copper distribution about the centre. Three failures are common: a heavy copper plane on one side and a sparse signal layer on the other; a different dielectric thickness above and below the centre; and a mixed stack where the PTFE sub-stack sits on one face. The last one is the hardest, because the two materials have different CTE and different cure behaviour, and the only real mitigations are to keep the RF material symmetric about the centre and to accept additional press cycles. How those cycles are sequenced is in lamination in high-frequency PCB manufacturing.

The single most consequential process fact about high-frequency stacks is that the bonding chemistry differs by family, and the temperature windows do not overlap enough for one press cycle.

So a board that mixes PTFE RF layers with FR-4 digital layers is built in sequence: press the PTFE sub-stack at its own temperature, then bond it to the FR-4 using a low-flow bondply at a temperature the PTFE can survive. Each additional cycle adds registration error — roughly ±25 µm per press — and cost. This is why a hybrid stack should be justified by something the design cannot get otherwise, and why the number of presses belongs in the quotation.

PTFE is soft, and under press pressure it thins permanently. A 4 % reduction in dielectric height takes a 50 Ω microstrip to about 48.8 Ω, and unlike an etch error it cannot be compensated afterwards, because the material does not spring back. The countermeasures are procedural: lower pressure (150–250 psi rather than the 250–350 used on epoxy), a thicker starting dielectric to absorb the thinning, and an impedance coupon pressed with the same recipe.

The same property explains why PTFE boards should not be re-pressed to correct a warp, and why a rework cycle that involves heating under pressure is riskier on PTFE than on a thermoset. A thermoset that has already cured is dimensionally stable; a fluoropolymer is not.

With the five layers described, the budget can be assembled. Thickness tolerance on a laminate is typically ±7–10 %, bondply adds its own ±10 % plus flow variation, and copper thickness contributes through the trace cross-section rather than through h. The combination decides the impedance window.

The first three combine randomly, so they add in quadrature: about 6.6 % in total for a 0.254 mm stack, which fits inside a ±10 % window and does not fit inside ±5 %. The last row does not combine randomly at all — it is a systematic error, and a systematic error of 22 % is not a tolerance problem but a drawing problem.

Consider a typical request: a four-layer board, RF on the top two layers, digital on the bottom two, 50 Ω microstrip, 0.5 mm pitch parts, expected volume in the hundreds.

The design arrives with a 0.254 mm RF core, a 0.56 mm trace and an assumption that h = 0.254 mm. The fabricator presses with 0.10 mm of bondply between the RF core and the ground plane below, because a four-layer hybrid needs that bond to survive two press cycles. The actual dielectric height becomes 0.354 mm and the same trace measures about 61 Ω: a 22 % error that no coupon tolerance can absorb.

Three corrections are available. Narrow the trace to about 0.38 mm, which restores 50 Ω but costs current capacity and puts the width closer to the etch floor. Use a 0.15 mm core with the same bondply, which brings h to about 0.25 mm. Or accept the impedance and specify the 61 Ω as the design target, which is legitimate only if the matching network is retuned for it. The first two are manufacturing decisions; the third is a design decision. What is not available is the original assumption.

Every stack that reaches a fabricator with an impedance target and a single thickness number is one of these cases waiting to happen. The stack-up method that avoids it — eight steps, each of which fixes one number — is set out in high-frequency PCB stack-up design, and the general anatomy of layers is in PCB structural layers.

The list is short because a stack review that takes an hour is an hour that will not happen. Five questions, each answerable from the drawing.

One. Is the impedance computed from the pressed dielectric height, including bondply, rather than from the core datasheet? Two. Is the press sequence stated, and does the number of cycles match the number of bond interfaces? Three. Is the copper foil type specified per layer, and is it the profile that the loss budget assumed? Four. Is the stack mirrored about its centre in material, thickness and copper distribution? Five. Is there a coupon on the panel, at the same location, measured with the same finish?

A stack that fails any of the five will still be built, and it will still pass its own coupon if the coupon was designed the same way. The failure appears as yield loss on the tune line or as a field return, both of which are more expensive than the review.

The original version of this guide was written for students, and the three mistakes below are the ones that show up in student designs most often. Each has a number attached, because the correction only sticks when the cost is visible.

Widening the trace to reduce loss. On a controlled-impedance line the width is fixed by the dielectric height. To widen a 50 Ω line you must thicken the core: at 10 GHz on Dk 3.38 the copper term falls from 0.19 to 0.095 dB/in between 0.254 and 0.508 mm, while the dielectric term stays at 0.13 dB/in and the board doubles in thickness. Adding a ground layer to fix crosstalk. A plane helps only if it is continuous under the aggressor and the victim, and if the return path is not forced to detour. A split plane is worse than no plane, because the return current takes the long way round and radiates. Ignoring the bondply. The 22 % error in section four comes from this one, and it is the most common cause of a first-article impedance failure on a board that was designed correctly in every other respect.

High-frequency lamination is not a mysterious craft; it is a stack of five tolerances that have to be added up before the panel is built. The core sets the width, the foil sets the conductor loss, the bondply quietly adds height that nobody counted, the mask shifts the mean by a few ohms, and symmetry decides whether the height stays uniform across a 600 mm panel. Three press families — 170–190, 190–200 and 260–300 °C — cannot be combined into one cycle, and PTFE thins about 4 % under pressure and does not recover, which is 50 Ω becoming 48.8 Ω.

XCE PCB reviews stacks against those five questions before quoting: 2 to 72 layers, panels to 600×1200 mm, impedance ±10 % with coupon data from centre and edge, PTFE and mixed stacks pressed in-house, samples in as fast as 24 hours, 5,000 m² of plant and 80+ engineers, more than 10,000 high-frequency builds since 2009, inspected to IPC-A-600G and IPC-6015. Cutting and measurement upstream of the press are covered in substrate cutting, and the differences between these stacks and an ordinary board are summarised in high-frequency PCB versus standard PCB.