High-Frequency PCB Design Steps: Seven Stages and the Numbers Behind Each

A high-frequency board is decided at the design stage, not on the fab floor. By the time artwork is released, three things are already frozen: the loss budget, the Dk basis used for every impedance calculation, and the tolerance stack that decides whether ±10% is even reachable. This is the seven-step sequence we see work, with the one number that has to be fixed at each step — and the ones that cannot be recovered later.

Almost every high-frequency board that disappoints in the field was electrically correct at incoming inspection. It passed continuity, it passed the impedance coupon, and it still drifted in phase, cracked a barrel after thermal cycling, or landed 150 MHz off the intended band. In each case the root cause was a decision taken weeks earlier, in a design file.

There are three irreversible decisions, and they are all made before the first panel is cut:

• Material and Df set the dielectric loss floor. No process tuning recovers loss that the laminate guarantees.
• The Dk basis sets every trace width on the board. Pick the wrong Dk number and the whole lot is offset the same way — which is worse than a random error, because it looks correct on every unit.
• Stack symmetry and via geometry set mechanical reliability. A fabricator can hold a tolerance, but cannot undo an asymmetric build on a laminate that expands at 200 ppm/°C in Z.

The seven steps below are ordered so that each one closes a decision the next one depends on. Step 3 (stack-up) is treated in depth in the stack-up design guide, and the fabrication side of the same project — the twelve process steps and the five that change for PTFE — is mapped in the high-frequency manufacturing process guide. This article is about what has to be settled before either of those can start.

Engineers usually pick a laminate first and then discover the budget does not close. Reverse the order: write the budget in dB, at the highest frequency, over the longest net, and let it choose the material.

For a homogeneous line (stripline), dielectric attenuation per unit length is close to:

α_d ≈ 2.6 · f_GHz · √Dk · Df   [dB per inch]

Microstrip reads slightly lower because part of the field sits in air, but the ranking never changes. Applied to the laminates in this series:

Two readings in that table are worth pausing on. The RO3010 row loses more per inch than RO4350B but less per wavelength: physical length shrinks with 1/√Dk, so at equal electrical length total dielectric loss depends on Df alone. That is why a high-Dk material is a size decision, never a loss decision. And the jump from 0.19 to 0.045 between RO4350B and 5880 is not a polish — it is roughly a 4× reduction in the part of the loss the laminate controls.

Then account for the part it does not control. Once dielectric loss drops to 0.035 dB/in at 10 GHz, conductor loss of roughly 0.04–0.07 dB/in for 1 oz copper becomes the majority of the total. On FR-4 the dielectric is about 95% of the loss; on 5880 the copper is over half. At that point foil roughness (VLP or HVLP), copper thickness and surface finish matter more than any further Df improvement — a fact that buyers rarely see on a datasheet comparison.

Four numbers decide the selection, and they are not interchangeable. The rest of the datasheet is detail.

Dk (process and design, see Step 3) sets geometry. Df sets the loss floor you just budgeted. TCDk sets phase drift over temperature — irrelevant for a short interconnect, decisive for a phased array. Z-axis CTE sets how much stress every plated barrel absorbs.

Two of these rows contain a hard gate rather than a trade-off. RO4003C carries no UL 94 rating while RO4350B is V-0, so any application with a flammability requirement removes 4003C regardless of its better Df; the physics behind that gap is the brominated flame retardant, whose polar groups raise Df — you cannot have both in this family (compared in detail in 4350B versus 4003C). And 5880’s Z-CTE of 237 is a manufacturing constraint disguised as a material property: it caps aspect ratio and plating ductility, not just loss.

TCDk values for the same group: RO4003C +40, RO4350B +50, RT/duroid 5880 −125 ppm/°C. Note the sign — 5880 is not the “temperature-stable” choice. It is the lowest-loss choice, and its Dk falls 2.5% across the −50 to +150 °C window. Step 5 quantifies what that does to phase.

Every laminate table has two Dk columns and they are routinely confused. Process Dk is the value measured on a test coupon at 10 GHz, the number a fabricator’s process control refers to. Design Dk is the wider-band value intended for field solvers and for designing across a band; it runs higher than process Dk because it includes the dispersion the application will actually see.

For RO4350B that is 3.66 against 3.48. Size a 50 Ω line with 3.48 and the finished board comes in about 1 Ω low, with electrical length roughly 1% short as well — small in isolation, but systematic across every net, and enough to move a narrowband filter or a patch antenna off centre. Two additional traps sit inside that same number:

• Thickness changes Dk. On 0.101 mm (4 mil) RO4350B, the specified process Dk is 3.36, not 3.48. Designing a thin RF layer with the standard value overstates impedance.
• Dk dispersion is real across the band. A model calibrated at 10 GHz and applied unchanged at 77 GHz will be optimistic about impedance and wrong about phase. Use the wideband model, not a single point.

Stack-up itself is the next irreversible decision, and on high-frequency laminates the governing rule is symmetry: identical dielectric thickness and copper weight either side of the centre line, and no unbalanced PTFE layer count. With Z-CTE in the 200 ppm/°C range, an asymmetric build bows during cool-down and leaves permanent stress in every barrel. Where the design mixes a high-frequency laminate with FR-4 to control cost, the prepreg choice at the interface becomes the yield factor — covered in the hybrid lamination process analysis.

Width and dielectric height set characteristic impedance, but the useful design work is in the sensitivity, not the nominal value. The table below gives 50 Ω microstrip geometry as a ratio, so it applies at any dielectric thickness and stays valid when a supplier changes core thickness.

Now the part most layouts never check. On a 0.254 mm RO4350B layer, a 50 Ω trace is 0.56 mm wide; ±25 µm of etch variation is ±4.5% of the width, and impedance moves about 0.6% for every 1% of width — so etch alone costs ±2.8%. The same ±25 µm on a 0.127 mm layer is ±8.9% of the width, or roughly ±5.5% of impedance. Thin dielectric does not just raise the field density; it converts the same etch tolerance into twice the impedance error.

The three random terms combine to about 6.6% against a ±10% window, which leaves very little room. The two systematic terms are worse, because they do not average out: a mask that is not in the model offsets every board by the same 2–6%. Design the stack with mask included and with the fab’s real etch compensation; the theory and the production side of this are covered in impedance control for high-frequency boards.

Length matching is necessary and not sufficient. Two effects make two traces of identical length behave differently, and both are visible only in phase.

Glass weave. On woven laminates the effective Dk under a trace depends on whether it runs over a glass bundle or a resin window, so a differential pair can accumulate intra-pair skew even when both members are the same length. The mechanisms differ by material: RO4000 series use 1080 and 1674 glass, where the finer 1674 weave narrows the bundle-to-window contrast, and PTFE materials split between woven glass (TLY-5) and random microglass (5880, effectively isotropic). Standard mitigations are to route at a small angle to the weave rather than parallel to it, to keep pairs on one glass style, and to hold intra-pair skew to a few picoseconds rather than to a millimetre target.

Dk drift with temperature. A 100 mm stripline at 10 GHz accumulates about 2,300° of phase on RO4350B and about 1,780° on 5880. Across the −50 to +150 °C span of the TCDk specification, RO4350B’s +50 ppm/°C adds 1% to Dk — roughly 11° of phase — while 5880’s −125 ppm/°C removes 2.5%, about 22° the other way. For a single link that is invisible. For a phased array or a delay-matched assembly it is the whole error budget, and it is why RF designers sometimes choose a higher-loss laminate with a flatter TCDk over the lowest-loss one.

Reference continuity. The advice to “dedicate one layer to ground” misses the point: every signal layer needs a continuous reference directly adjacent to it, and an RF trace must never cross a plane split. When a return current is forced to detour around a split, the loop area grows, radiation rises, and the trace behaves like an unintentional antenna at exactly the frequency band it was designed for.

These three are usually handed to the fabricator as process choices. They are not: each one is fixed by geometry or by the layer stack, and each one shows up as loss or as a resonance.

Via stub. A through via in a 1.6 mm board leaves a stub that behaves as a quarter-wave resonator; with an effective Dk near 4 that resonance lands close to 23 GHz (18–19 GHz at 2.0 mm, about 12 GHz at 3.2 mm). Below that frequency the stub is a mild discontinuity; at and above it, it is a notch. The design responses are blind or back-drilled vias, or routing the high-frequency layers near one surface so the stub stays short.

Via geometry and plating. Aspect ratio is depth over finished diameter: a 0.2 mm via in a 1.6 mm board is already 8:1. On PTFE builds with Z-CTE above 200 ppm/°C we hold critical vias at or below 6:1 and specify high-ductility plating (≥20% elongation), because the barrel has to stretch with the laminate, not resist it.

Surface finish. At 10 GHz the skin depth in copper is 0.65 µm and in nickel 1.33 µm. An ENIG nickel layer of 3–6 µm is therefore several skin depths thick, so the RF current travels in a metal with about a quarter of copper’s conductivity. ENIG remains the right choice for fine pitch, assembly durability and shelf life; on long millimetre-wave runs it is worth costing immersion silver or OSP, which put the current back on copper.

Solder mask. A 20–25 µm mask layer over microstrip lowers impedance by 1–3 Ω. Design with it in the model, or open the mask over the RF trace — which also removes the mask’s loss contribution and its variability. The finish and mask trade-offs on a mixed stack are examined in the hybrid ENIG analysis.

Simulation closes the design; it does not verify the product. A 3D field solver (HFSS for structures and antennas, ADS for circuit-level RF) will answer the questions the layout cannot: launch discontinuities, cavity resonances, coupling between adjacent RF chains, and the effect of the enclosure. Three settings decide whether the answer is worth anything:

• Import the stack the fabricator will build, with its real dielectric thicknesses and copper weights — not the nominal catalogue stack.
• Use a roughness-aware conductor model. Below a few gigahertz foil roughness is a rounding error; on a 0.0009-Df laminate at 30 GHz it is a first-order term.
• Include mask and finish, or the systematic offsets in Step 4 reappear as a “model error”.

Then insist on the physical proof: a controlled-impedance coupon on the production panel, measured by TDR against the ±10% band, with the coupon geometry matching the product geometry (same line type, same width, same reference distance). A coupon that is convenient to measure but not representative proves nothing. For first articles, this is also where a fast build pays for itself — XCE PCB runs 2–72 layers with impedance coupons on every RF lot and samples in as fast as 24 hours, so the stack can be validated before the design is frozen into tooling.

None of these is exotic. All seven are decided in a file, and six of them are invisible on a finished, functioning board.

A high-frequency RFQ that arrives with a complete package comes back with a firm impedance commitment instead of a disclaimer. The minimum set:

XCE PCB builds to this package daily on Rogers, Taconic and F4B laminates: 2–72 layers, impedance ±10% with coupons on RF lots, panels to 600 × 1200 mm, a 5,000 m² facility with 80+ engineers, and samples in as fast as 24 hours. If a stack is still open, the fastest route is to send the loss budget and the impedance table and let the laminate be chosen against them — the material comparison in the RT/duroid 5880 laminate guide is a useful starting point for the low-loss end.