PCB Through Holes: Properties, Functions and the Two Devices Sharing One Name

A through hole is the simplest feature on a PCB and the one with the most requirements attached. It has to be drilled to one diameter and finished at another, plated to a thickness that survives thermal cycling, surrounded by enough copper to survive registration error, and — if it carries a signal — short enough not to resonate. The first thing to separate is which of two devices you are specifying: a component hole or a signal via. They share a drill and nothing else.

Every plated through hole is a hole through the board with copper on the wall. What it is for divides it into two families with almost no requirements in common:

The NPTH point deserves a line of its own: a mounting hole is not a plated through hole, and specifying 25 µm of copper in it costs money and creates a short risk if a screw or a standoff touches a ground plane. Mark non-plated holes explicitly on the drill drawing, with their own diameter and tolerance.

The two HF-specific companions to this article — hole types and hole size — cover blind, buried and microvia variants and the sizing trade-offs in RF boards. What follows is the through hole as an element.

Plating adds metal to the wall, so the hole you drill is larger than the hole you get. At 25 µm per side, the finished diameter is 50 µm smaller than the drill: a 0.30 mm finished hole is drilled at 0.25 mm. Two consequences follow, and both cause real errors.

First, the drawing must say which dimension it means. A drill file carries drill diameters; a mechanical drawing usually carries finished diameters; a component datasheet carries the lead diameter. When those three are mixed, the part either does not fit or fits loosely enough to wick solder through the barrel.

Second, the real constraint on how small a hole can go is not the drill bit but the aspect ratio — board thickness divided by drill diameter. Plating chemistry has to push fresh electrolyte and anodes into the hole and pull depleted solution out; beyond a certain ratio the copper at the centre of the barrel thins out.

Eight to one is the normal ceiling for standard chemistry; ten to one needs special plating; PTFE materials are usually held to six to one because the barrel has to survive far more Z-axis movement. A 0.20 mm via in a 1.6 mm board is already at the standard limit, which is why dense designs move to thinner boards or to sequential lamination instead of smaller drills.

The copper in the barrel is what makes the hole a connection, and its quality is specified in ways that do not appear on a drawing. IPC-6012 sets the minimums: for Class 2, 20 µm average with 18 µm minimum; for Class 3, 25 µm average with 20 µm minimum. The average/minimum pair matters because barrel copper is thinnest at the middle of the hole and thickest at the surface — a measurement taken at the top of the hole flatters the board.

Thickness is only half of it. The other half is ductility: the barrel must stretch with the substrate as the board heats, and the substrate moves a lot. Across a 125 °C excursion a 1.6 mm thick PTFE board expands about 47 µm in Z (237 ppm/°C), a hydrocarbon laminate about 6 µm, FR-4 somewhere in between depending on whether Tg is crossed. The copper has to absorb that without necking, which is why high-ductility chemistry with 20% or more elongation is specified for PTFE and for thick boards. The plating article covers the process side.

Before plating there is the wall itself. Drilling leaves smear — resin reflowed by friction heat — and smear blocks the copper-to-inner-layer connection. Permanganate desmear handles epoxy; PTFE needs sodium naphthalenide or plasma, because permanganate simply does not attack it. A via with inadequate desmear passes continuity test and fails in the field, which is why cross-sectioning on a first article is not optional.

Annular ring is the copper left around the hole after drill tolerance, layer registration and pad definition error have all been applied. Its minimum is a specification, not a preference: 0.05 mm is the usual floor, and Class 3 work often calls for 0.05 mm on internal layers and more on external pads that will be soldered.

The budget behind that number:

• Drill position ±0.05 mm on a modern CNC with a good stack.
• Layer-to-layer registration ±0.05–0.075 mm, worse on thick boards and on PTFE because of expansion during lamination.
• Pad image tolerance from etch or LDI, a few tens of microns.

Those are independent errors, so the ring does not simply subtract; it accumulates as a root-sum-square, which is why a 0.15 mm designed ring survives a 0.05 mm minimum. The point to carry into layout is that the drill-to-copper relationship, not the drill diameter, is what breaks first on a dense board. Breakout — the barrel touching or crossing the pad edge — is a Class 3 reject and a Class 2 concern.

A via is a short piece of coaxial line with a discontinuity at each end. Three numbers describe it well enough to design with:

Stub resonance is where the electrical and mechanical descriptions of a through hole collide. Electrically, the ideal via is the height of the connection it makes: an outer-to-inner-layer connection on a 3 mm backplane should be 0.5 mm long, not 3 mm. The excess — the stub — is a resonant cavity, and at the resonant frequency the via presents a notch in the channel. Two fixes: back-drill the excess (residual stub held to 0.2–0.3 mm), or build the connection with blind/buried vias so the barrel never passes through layers it does not need.

For ground, the rule is not one via per signal via but a return path that is short at the frequency of interest: two ground vias on either side of a signal via, as close to the barrel as the pad geometry allows, both connected to the same plane the trace references.

A through hole conducts heat only when it is part of an array and connected to something that spreads it. A single via in a thermal pad moves a negligible fraction of the dissipation; a 5 × 5 array at 0.8–1.0 mm pitch is a genuine heat path, and it is usually the only one available on a laminate whose dielectric conducts 0.2–0.7 W/m·K.

The numbers that guide the array: 0.3 mm drill, 25 µm wall, 0.8–1.0 mm pitch, all connected to a copper plane or a spreader on the other side. Each via of that size carries roughly 1 A at a 10 °C rise, so an array also doubles as a current path for a power pad — a useful side effect rather than a design goal.

Two cautions. Thermal vias must avoid nets that are already tuned; a via that lands in a matching network changes the network. And on a high-frequency board, thermal vias are part of the RF ground, so their placement is constrained by return-path geometry as well as by heat.

Through holes do not strengthen a board. A drilled hole is a stress concentrator, and a plated barrel is the least ductile feature in the Z direction. What through holes actually do mechanically is three narrow things: they retain leaded components, they provide the solder joint that holds them, and — in the specific case of a filled and capped via in a pad — they provide a flat, solderable surface where a via would otherwise wick solder away from the joint.

Everything else is a failure mode: barrel cracks from Z-axis expansion, pad lift from rework heat, corner cracks at the drill exit from poor hole quality, and interfacial separation when plating adhesion is weak. Each maps to a process cause, which is why the drill and plating specifications are written the way they are.

The drilling side of these — bit geometry, hit counts, entry and exit materials, burr limits — is covered in the drilling process article.

• Which diameter you mean — drill or finished — for every hole, and the plating thickness assumption (25 µm per side).
• PTH or NPTH for every hole, with NPTH on its own layer and its own tolerance.
• Annular ring minimum, and whether breakout is permitted on any layer (it usually is not).
• Aspect ratio for the thickest section the hole passes through — and if it exceeds 8:1, say so explicitly so plating is planned.
• Via treatment: tented, plugged, filled and capped, or open — each has a different process and a different cost.
• Back-drill requirement where stub length matters, with the residual stub dimension and which layers it applies to.
• Class of acceptance: IPC-6012 Class 2 or Class 3, because it changes the plating and ring minimums.

For how the stack around the hole is arranged, the stack-up guide covers layer pairing; the specification items above are what turns that arrangement into something a fabricator can inspect.

The through hole is where geometry, plating, registration and RF behaviour meet in one feature 0.3 mm across. Specify it as two devices — a component hole with solderability requirements, or a signal via with an electrical budget — and most of the confusion disappears. Then fix the four numbers that matter: drill versus finished diameter, barrel thickness and ductility, minimum annular ring, and stub length where the frequency makes it relevant.

XCE PCB drills and plates the full range — 2–72 layers, aspect ratios planned per stack, PTFE-qualified desmear and high-ductility plating, impedance held to ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours.