Multilayer vs Single-Layer PCB: The Line Is a Reference Plane

The usual comparison sets single-layer boards against multilayer ones and lists cost, density and signal quality as if layer count were the variable. It is not. The variable that decides whether a board can carry a controlled-impedance signal, hold an edge together or pass an emission test is whether the signal has a continuous reference plane underneath it — and a single-sided board has none. That single fact explains most of the differences usually attributed to layer count, including several that the original version of this article stated the wrong way round.

A microstrip needs two conductors: the trace and a plane beneath it. Without the plane there is no defined characteristic impedance, no controlled return path and no way to predict crosstalk. A single-sided board has one copper layer, so every trace on it is either a coplanar structure with a return that is itself a trace, or an uncontrolled conductor whose impedance depends on what is near it.

This is why the comparison is better made between board structures than between layer counts. A two-layer board with a solid ground on the back is a perfectly good controlled-impedance platform for microstrip; a four-layer board whose inner layers are both signal layers, with no plane, is not. The layer count is a proxy for the property that matters, and a poor one.

The rule that follows is worth stating in the form that survives review: a stripline needs two planes and a microstrip needs one, so a stack with n signal layers needs n+1 planes if all of them are to be referenced. A four-layer board cannot contain a stripline at all, because it has only one interior pair of planes at best; that is a geometric fact and not a matter of manufacturer capability.

Four capabilities disappear when the plane disappears, and each has a measurable consequence.

Impedance. Without a plane, ε_eff is dominated by the air above the board and by whatever is behind it. A 0.5 mm trace on 1.6 mm FR-4 has an effective dielectric constant somewhere between 1 and 4.2 depending on how it is mounted, which is a spread wide enough to make a 50 Ω design meaningless. Coplanar geometry with side grounds recovers some control, but the grounds are traces, so their own inductance is part of the circuit.

Return path. Return current follows the lowest-impedance path, which at high frequency means the path closest to the signal. On a single-sided board the closest return is a neighbouring trace or the chassis, and neither is where the designer put it. The result is a loop area set by the mechanical assembly, which is why single-sided boards radiate in ways that no layout change fixes.

Crosstalk. With no plane, coupling between two parallel traces is governed by their mutual geometry in free space rather than by a controlled field distribution. Spacing helps, but the field is not confined and the coupling falls far more slowly with distance than it does over a plane.

Stripline. The best isolation structure in PCB design — a trace buried between two planes — is unavailable, so there is no way to build a line that does not radiate at all. Where a design needs an isolated or a very low-emission path, layer count is not a preference, and the difference between the two structures is worked through in microstrip and stripline design.

The other common claim is that multilayer boards hold more circuitry. True, but the multiplier is smaller than the layer ratio, because routing capacity per layer falls as layers are added: inner layers cannot be probed, cannot be reworked, and must obey plane clearances.

The four-layer step deserves attention because it is the largest single jump and it is not caused by the two extra copper layers. It is caused by the planes: once a solid reference exists, traces can be routed at 0.1 mm and 0.1 mm spacing without the impedance drifting, and the escape from a dense component becomes possible at all. That is the mechanism behind a capacity jump of four to five times on a board with twice the copper.

Price steps do not track layer count evenly. The first step is small, the second is large, and after that each pair of layers adds less proportionally.

The step from two to four layers is the one that catches budgets, because it is a factor of about 1.6 for a factor of two in copper layers, and it arrives at the same moment as the requirement for a controlled-impedance specification. The step from four to six is proportionally smaller. The implication is straightforward: if a design has to move off two layers for impedance reasons, going to four is the cheapest way to get there, and stopping at four is usually better than moving to six for density alone.

Lead time has a different structure from price, because it is dominated by press cycles rather than by area. A four-layer board needs one lamination cycle, a six-layer two, and each cycle adds ramp, dwell and controlled cooling. That is why an eight-layer board costs proportionally less than it takes proportionally longer: press time is a queue, and queues do not scale with panel area.

The claim that multilayer boards dissipate heat better is true on FR-4 and false on low-loss RF laminates, and the difference is worth a number because it changes material selection.

On an FR-4 board, adding inner copper gives heat somewhere to spread, and that is genuinely useful. On a PTFE board, adding layers means adding dielectric in the vertical path, and the vertical path is the one that matters: a component on the surface has to get its heat through the laminate above the first plane, and no amount of copper below that plane shortens the journey. Adding a plane helps only if it is directly beneath the heat source and connected to it by thermal vias, whose current and thermal capacity both follow from their wall area rather than from their count — the geometry is set out in PCB through hole.

So the correct statement is narrower than the usual one: multilayer construction improves heat spreading laterally through planes, and through vias when they are placed for it; it does not reduce the vertical thermal resistance of the dielectric, and on low-k materials it makes the vertical path worse by adding thickness. For a device dissipating 10 W/cm² the difference between 0.30 and 0.20 W/m·K is a 42 K penalty, which is a material decision rather than a stack decision.

Bending stiffness of a plate rises with the cube of thickness, so a thin multilayer board can be less stiff than a thick two-layer board even though it has more layers. A 0.6 mm board has about 5 % of the stiffness of a 1.6 mm board of the same material, which matters for connectors and for anything assembled with a press-fit or a card guide.

The same relationship is why thin multilayer boards warp. Warp is driven by asymmetry — copper distribution, stack symmetry, and the difference in cure shrinkage between a core and its bond lines — and a thin board has less stiffness to resist the resulting moment. A 0.4 mm eight-layer board with an asymmetric copper distribution can bow by more than the coplanarity allowance of a fine-pitch connector, which is why the panel design and the copper balancing are part of the electrical design rather than a cosmetic step. The structural view of the stack is covered in PCB layer structure.

None of the above makes single-sided boards obsolete. They are correct wherever the circuit has no controlled-impedance requirement, no emission requirement that a loop area would violate, and a low enough component count that one layer can route it.

The pattern that fits is: low frequency, low power, mains-referenced or battery, with a chassis that provides the return. Domestic controls, mains switches, simple lighting drivers, appliances and low-cost sensors all sit here. The engineering discipline that makes them work is different from multilayer design: current loops are kept small by placement rather than by planes, high-current paths are wide and short, and the return is designed as a physical wire or chassis connection rather than assumed.

The trap is at the boundary. A single-sided board with a 20 MHz microcontroller and a switching regulator is not a simple board: the switching loop radiates, the MCU edge rates are fast, and there is no plane to control either. The correct upgrade at that boundary is not more layers for density but a two-layer board with a solid ground, which solves the emission problem for a fraction of the cost of a four-layer build.

Four situations force the decision, and they are all electrical rather than density-driven.

The third row is where high-frequency work stops being a cost question. A stripline needs a plane above and below, which means four layers minimum for one stripline layer pair and six for two. On a board with two RF chains that must not talk to each other, the isolation requirement fixes the layer count before anyone looks at the BOM. The density argument for the same decision is set out in HDI PCB performance, where the layer count is driven by escape rather than by isolation.

The original comparison was conventional and, in four places, backwards.

Five questions, asked in order, produce the structure without a debate about layer count.

1. Is there any net with a controlled impedance requirement? If yes, a solid reference plane is mandatory and the minimum is two layers with a ground. 2. Is there any emission or susceptibility requirement that a loop area would violate? If yes, every signal layer needs a plane beneath it, which means four layers for a two-signal design. 3. Do two RF chains need isolation from each other? If yes, stripline is required, and that fixes four layers per stripline pair. 4. Does the escape from the densest component close on the available signal layers? If it does not, the answer is HDI rather than more layers, because additional layers do not create escape capacity at a 0.5 mm pitch. 5. Does the mechanical envelope allow the thickness the answer implies? A 0.6 mm board has 5 % of the stiffness of a 1.6 mm board, which rules out press-fit connectors unless there is a stiffener.

Only after those five does price enter, and when it does, the comparison is between two structures that both work. Comparing a working four-layer board with a non-working single-sided one is not a cost comparison; it is a comparison between a product and a prototype. The stack that results is then developed into a drawing in the way described in high frequency PCB stack-up design, and the four-layer case specifically is covered in four-layer double-sided high-frequency PCBs.

The difference between a multilayer high-frequency board and a single-layer board is not the layer count; it is the presence of a continuous reference plane. Without one there is no controlled impedance, no defined return path, no stripline and no practical way to confine a field, which is why the claim that single-sided boards suit simple high-frequency circuits is the wrong way round. With one, a two-layer board is a perfectly usable 50 Ω platform.

The economics do not track layer count evenly. Moving from two to four layers costs about 1.6 times for twice the copper, and it delivers the largest single jump in usable routing capacity — four to five times — because the planes make fine-line routing possible. Moving from four to six adds proportionally less, and past the point where the routing closes, additional layers buy nothing but press cycles and aspect ratio.

The thermal claim needs the most correction: multilayer construction spreads heat laterally, but the vertical path is set by the dielectric, and on a low-loss laminate that path is the worst in the catalogue. 0.254 mm of 5880 is 12.7 K·cm²/W, equivalent to several hundred millimetres of copper. XCE PCB builds both ends of the range — 2 to 72 layers, impedance ±10 %, panels to 600×1200 mm, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015 — and for a design that has to choose between a low-cost conventional board and an RF stack, the trade-offs are set out in high-frequency PCB versus standard PCB.