Microstrip and Stripline Design in High-Frequency PCB Production

Microstrip and stripline are the two transmission-line structures every high-frequency PCB is built from, and most of the decisions that determine their impedance are made before fabrication starts. This article walks the design sequence from structure choice to release for production, and then states what the fabricator must actually control — trace width, dielectric height and copper thickness — because the impedance of a finished line is set by those three numbers, not by the simulation that predicted them.

Both structures need correcting from the usual short definitions, because the errors compound later.

Microstrip is an outer-layer conductor running over a single reference plane. The field lives partly in the laminate and partly in air, so the effective dielectric constant is lower than the laminate Dk — on a Dk 3.66 material, roughly 2.85 for a 50 Ω line. Signals travel faster and structures are cheaper to etch, but the field is exposed: any solder mask, conformal coating or metal object above the trace changes its impedance.

Stripline is not “two parallel conductors”, as it is sometimes described. It is a single conductor buried between two reference planes, fully inside the dielectric. The field is homogeneous, the effective Dk equals the laminate Dk, radiation is zero and isolation from other layers is excellent. The price is geometry: at the same laminate thickness a stripline must be much narrower, which makes it far more sensitive to etch error.

The structural comparison frames every step that follows: microstrip is cheap, fast and exposed; stripline is quiet, slow and intolerant of manufacturing error.

Most RF work targets 50 Ω single-ended; 75 Ω survives in video and some antenna feeds, and 100 Ω paired lines handle most differential standards. What matters more than the number is the tolerance window, because the window is what the fabricator quotes against.

A ±10% window on 50 Ω spans 45–55 Ω, and each physical parameter claims a share of it. On a 0.254 mm hydrocarbon laminate, dielectric thickness ±10% alone moves a 50 Ω microstrip by about ±6% — most of the window. Etch error of ±25 µm adds roughly ±2.8% on a 0.56 mm line, and a ±0.05 Dk spread adds under 1%. The contributions add in quadrature to roughly 6.6%, which is why the impedance budget belongs to the stack-up, not to the schematic.

Define the window per line class at this step, in writing. A fabricator who receives “50 Ω” without a window will apply a house default, and the house default may not match what the transceiver at the end of the line assumes.

The choice is usually made by one dominant requirement:

Count reference planes before committing: every stripline layer needs a plane on both sides, so n stripline layers require n+1 planes. A four-layer board offers two impedance layers, both microstrip; meaningful stripline capability starts at six layers. This arithmetic is the layer-count rule described in the design-steps guide.

Width and spacing come from closed-form equations or a field solver, but the input Dk must be the one the fabricator holds to. Laminates publish a process Dk at one frequency and a design Dk across a band, and they differ: RO3010 is 10.2 as processed and 11.20 in design tables. Solving with the wrong one shifts every electrical length by several per cent, as explained in the parameter breakdown.

Two consequences worth noting. On high-Dk material the 50 Ω trace is barely wider than the dielectric is thick, so the same ±25 µm etch variation is a much larger percentage of the line — high-Dk materials are size decisions, not low-loss decisions. And because microstrip sits in mixed dielectric, anything deposited on the trace shifts it: 25 µm of solder mask over a 0.127 mm PTFE microstrip pulls 50 Ω down by roughly 3 Ω, while the same mask on 0.508 mm moves it under 1 Ω. Model the mask, or specify an opening over the RF trace.

Short traces matter, but the reference plane matters more. Three routing rules that production cannot repair afterwards:

• Never cross a plane split. A signal crossing a gap in its reference plane has no defined return path; the return detours and the crossing point becomes a radiating, dispersive discontinuity. Route around, or add stitching capacitance at the crossing.
• Keep spacing at three dielectric heights or more between RF lines. Crosstalk is set by the s/h ratio, not by absolute spacing: on thin laminates the field is confined close to the trace, so 3×h is usually enough isolation; on thick dielectrics the same absolute distance couples far more.
• Price the via before using it. A through-via on a 1.6 mm board leaves a stub resonating near 23 GHz — on a 2.0 mm board near 19. Below those frequencies the stub is a small parasitic; above, it is a notch in the passband. Back-drilling or blind vias are the fix, and both cost money the layout should have anticipated.

Layer transitions on stripline runs deserve special attention: each transition microstrip-to-stripline adds a via discontinuity, and a feed network built on inner layers can accumulate several. The loss budget in the next section is what should have priced those vias.

Solvers such as HFSS or ADS are standard at this step, but the model that predicts the measured board is the one that includes the as-built geometry, not the nominal layout:

• The finish, because it is the conductor. At 10 GHz the skin depth in copper is 0.65 µm, and the 3–6 µm nickel layer of an ENIG finish is where the current actually flows, at twice the surface resistance of copper. On a low-loss laminate such as 5880 or TLY-5, where copper loss already dominates the dielectric term, ENIG can add 30–50% to insertion loss; on FR-4 it changes almost nothing.
• The mask, as above — 1–3 Ω on thin microstrip, and its own loss tangent of 0.02–0.03 is twenty times the laminate’s on a low-Df material.
• Copper roughness. On low-loss laminates the conductor term is 0.04–0.07 dB/in at 10 GHz, so foil type (standard, RTF, VLP) is no longer a procurement detail.

Then record what was modelled. The single most common simulation-versus-measurement gap on high-frequency work is a model of bare copper compared against a finished, masked board — a gap of several ohms that looks like a fabrication error but is a modelling choice.

The design fixes geometry; three process numbers decide whether the finished line meets it:

The fabricator verifies these on a coupon in the same lamination cycle as the product, measured by TDR — the closed loop described in the impedance-control guide. A designer can shortcut surprises by stating the tolerance window, the copper weight and the mask allowance explicitly in the design files.

Material properties move with temperature, and the effect that reaches the system is phase, not attenuation. A 100 mm stripline at 10 GHz carries between roughly 1,800 and 2,300 degrees of accumulated phase; a TCDk of +50 ppm/°C across a −50 to +150 °C range shifts it by about 11 degrees, and a negative-TCDk PTFE by about 22.

For radar, phased arrays and any beam-forming network, 11–22 degrees of drift is a calibration item, not a footnote. The mitigation is material selection at the start — matched TCDk across the materials in one stack — because nothing in fabrication corrects it afterwards. Designers working across temperature should treat TCDk as a first-class stack parameter, as covered in the impedance and layer-stack guide.

The standard list of “issues and solutions” is mostly right, but the fixes are frequently stated at the wrong level. The table re-anchors each one:

Microstrip and stripline design is where a high-frequency product is won or lost, and the loss usually arrives as an unmodelled real-world layer: the mask, the finish, the via stub, the pad. The design sequence — structure choice, impedance window, width from the right Dk, reference-aware routing, as-built simulation — is only half the work; the other half is handing the fabricator a written tolerance window and agreeing how it will be verified on the finished board.

XCE PCB fabricates microstrip and stripline designs on Rogers, Taconic and F4B laminates with coupon TDR verification in the product’s own lamination cycle: 2–72 layers, impedance ±10%, panels to 600 × 1200 mm, 5,000 m² of production space and 80+ engineers, with samples in as fast as 24 hours.