Role and Key Considerations for Resin Plugging in High-Frequency Circuit Boards

“Resin plugging” is used on datasheets, drawings and purchase orders to mean at least four different processes, and the difference between them is the difference between a board that survives assembly and one that fails at reflow. Before any discussion of resin chemistry, coefficient of thermal expansion or grinding depth, the process has to be named correctly. This article starts there, then sets out what the plug is actually doing in a high-frequency stack and the numbers that decide whether it works.

A via that is merely covered by solder mask is tented. A via with resin forced into it and nothing on top is plugged. A via filled and then covered by mask is filled and covered. A via filled, planarised and plated over as a pad is filled and capped. The four have different flatness, different thermal behaviour and very different cost, and the standard that separates them is IPC-4761, which defines the via protection types by what happens on the surface rather than by what is inside the hole.

The distinction matters because the reasons for plugging are not the same in each case. Tenting exists to stop solder wicking during assembly. Plugging exists to stop the same wicking while leaving a surface that can be printed on. Filling exists to remove the cavity that causes an impedance discontinuity and a stub. Capping exists to create a flat pad over the via so that a component can be placed on it. When a drawing says “resin plugged” without naming the type, a fabricator will choose the cheapest interpretation that still looks reasonable, and the assembly house will discover the difference.

Two consequences follow immediately. The first is that most of the “high-frequency” benefits claimed for resin plugging — the removal of a stub, the removal of an air cavity — require Type V or better, because a mask plug leaves a dielectric discontinuity inside the hole. The second is that only Type VII gives a surface flat enough to place a land on, and Type VII is the most expensive and the one most sensitive to board thickness. Every consideration below is stated against a type for that reason.

Five roles are usually listed for resin plugging, and they divide cleanly into electrical, mechanical and assembly functions. Separating them matters because a design that needs one of them does not automatically need the others, and the cheapest correct type is the one that delivers only what is required.

The stub role deserves the arithmetic, because it is the one that is argued about in millimetres rather than decibels. A through via in a 1.6 mm board behaves as a shorted stub of roughly that length, and a quarter-wave resonance at 23 GHz puts a null in the transmission where a design may need to pass a harmonic. Shortening the board helps only a little; removing the stub removes the resonance. What the fill does not do is shorten the via, so the improvement is from the discontinuity disappearing rather than from a shorter path.

The most common sentence in a plugging specification is that the resin’s CTE should be close to that of copper and the substrate. On FR-4 that is achievable. On a PTFE high-frequency board it is not, because the substrate’s own Z-axis CTE is an order of magnitude away from copper and no plugging resin comes close to it either.

Read the last two rows as a stress statement rather than a materials remark. In a PTFE board at reflow, the laminate around the via expands about 80 µm while the cured plug expands about 17 µm, so the plug is left behind and the barrel has to accommodate the difference. That is why the plating elongation requirement (20 % or more) and the aspect-ratio ceiling (6:1) matter more on a PTFE board than the plugging resin’s own CTE, and why a resin chosen to match copper perfectly would not solve the problem.

The other side of the same coin is cure shrinkage. A plugging resin shrinks on cure, and the shrinkage is restrained by the barrel, so the stress appears as a tensile load on the wall and as a depression at the surface. Both are manageable at 1.6 mm and neither is manageable at 0.203 mm, which is the subject of why resin plugging is not feasible on a 0.203 mm high-frequency board.

Three numbers decide whether a filled via is acceptable, and each one fails in a different place. Voids fail at reflow. Depression fails at paste printing. Protrusion fails at mask adhesion and at the assembly coplanarity check.

The 25 µm depression limit is worth putting in context, because it is often repeated without a reason. At 0.5 mm pitch a stencil aperture is around 0.25 mm square and the paste deposit is 0.10–0.12 mm; a 25 µm dish in the middle of that area removes something like a fifth of the paste volume at the point where the joint forms. That is the mechanism behind the “open joint under a BGA that looked fine on X-ray” failure, and it is why Type VII exists as a separate category rather than as a variant of Type V.

The plugging step has two legitimate positions and one illegitimate one. The choice is driven by whether the fill has to be capped, and by whether the outer-layer pattern already exists.

The cap sequence is the one that catches design teams, because the extra plating is a thickness change on the outer layer. A 50 Ω line on the outer layer that was compensated for 35 µm copper is now 55–60 µm of copper at the cap, and the etch compensation for the whole outer layer has to change with it. This is not a manufacturing inconvenience; it is an impedance item, and it belongs in the same review as the stack. The interaction between plating thickness and line width is set out in common impedance designs and layer stacks.

Filling is a printing process with a vacuum assist, and like every printing process it depends on the geometry of the aperture. A shallow hole fills easily and empties easily; a deep, narrow hole traps air at the bottom and resists the squeegee. In practice a vacuum-assisted fill is stable up to about 8:1 on a hydrocarbon board and starts to show voids beyond 10:1, while on PTFE the softer wall and the rougher, activated surface change the flow rather than the ratio.

Two geometry details are routinely missed. The first is the barrel shape: a drill with a worn edge produces a tapered hole, and a tapered hole fills from the wide end and traps air at the narrow end. The second is the annular ring, because the stencil aperture is limited by the pad, not by the hole; a 0.25 mm hole on a 0.45 mm pad leaves 0.10 mm of ring and a stencil aperture that is only slightly larger than the hole, so the paste volume available is marginal.

The drilling side of this is in drilling high-frequency PCB, and the plating side in plating high-frequency PCB. What belongs here is the rule: if the ratio is above 6:1 on PTFE, the fill should be qualified on a test panel before it is specified on a product drawing, because a void rate measured on a 1.0 mm board does not transfer to a 2.4 mm one.

Plugging resins are sold on a datasheet with a dozen properties, and three of them decide the outcome. Thermal resistance above the reflow peak is first: a lead-free profile touches 245–260 °C, and a resin that decomposes or outgasses there will blister the cap. Volume shrinkage on cure is second, because it converts directly into depression and into tensile stress on the barrel. CTE above Tg is third, and it is the one that gets the least attention — below Tg most filled epoxy systems are comfortable, and above Tg the coefficient roughly triples.

What is not on the datasheet and matters just as much is the fill loading. A resin with a high silica loading has a lower CTE and a lower shrinkage, which is good, and a higher viscosity, which makes a deep via harder to fill. The two effects trade against each other at a specific hole geometry, which is why the same resin can be excellent at 0.3 mm diameter and poor at 0.15 mm.

For a high-frequency board there is a fourth consideration that is usually overstated and occasionally decisive: the dielectric constant of the cured resin. A filled via whose resin has Dk 4.0 in a laminate of Dk 3.0 is a small discontinuity; one with Dk 6 is a larger one. At 10 GHz and above, a filled via that is not capped is a dielectric plug in the current path, and the difference between a good and a poor resin shows up as a small reflection rather than as a failure.

Most plugging problems are designed in. Five rules remove most of them, and none of them costs electrical performance.

Keep the ratio inside 6:1 on PTFE, by reducing board thickness or increasing the hole, rather than by asking the fill to do something the geometry does not allow. Give the pad a ring — a stencil aperture that is only 0.05 mm larger than the hole cannot deliver enough paste — and prefer 0.10 mm per side. Do not put a plugged via under a fine-pitch land unless it is Type VII, because a Type V fill plus mask is not flat enough for 0.4 mm pitch. Keep plugged vias out of the RF field where possible: a via in a ground plane carrying a return current is not the place to introduce a dielectric discontinuity if a plated-through hole with a short stub would do. And state the type on the drawing, with the depression limit, because a drawing that says “resin plugged” will be quoted as Type II and delivered as Type II.

The interaction with the rest of the via design is in PCB through holes, and the HDI case — where via-in-pad is not optional — is in the HDI production process.

A filled via that blisters at reflow is usually blamed on the resin, and the cause is usually the bake schedule or the storage between plugging and lamination. A cured plug is a polymer with an equilibrium moisture content, and the laminate around it holds moisture too; on a PTFE board the laminate is nearly immune at 0.02 % absorption, so the moisture that matters is in the plug and in the bondply, not in the substrate.

Two practices follow. The panel should be baked before plugging, so that the fill is not competing with residual moisture in the hole, and baked again before any subsequent press or mask cure if it has been exposed to workshop humidity for more than a shift. The bake has to be matched to the material: a standard FR-4 core at 120–150 °C for 2–4 hours is normal, and a PTFE stack does not need it, so the schedule belongs on the traveller rather than in a general procedure.

The second practice is storage discipline between steps. A plugged panel waiting for planarising in a humid room is accumulating exactly the moisture that will expand at 250 °C, and the defect will appear as a blister around the via — which is the one place a blister is guaranteed to be interpreted as a plugging failure even when the plug is sound.

The acceptance method for a filled via is a microsection through the via centre, and its limitation should be stated as plainly as its value. A section proves the fill quality at the plane that was cut. It says nothing about the via 3 mm away, and nothing about the void that sits off-centre in the same via.

Three practices make the section more representative. Cut the via that the process is least likely to fill — the smallest diameter, the thickest board, the one nearest a panel edge, where the press and the printer both behave worst. Cut it after thermal shock rather than before, because the interface separation that matters appears after the stress. And keep the section as a process record with the lot number, so that a later failure can be compared against the fill that was accepted at the time.

Two non-destructive options supplement the section without replacing it: X-ray, which shows void distribution across the whole panel but not the interface, and TDR on a coupon containing a filled via, which shows the impedance improvement the fill was supposed to deliver. If the TDR trace shows the discontinuity still present, the fill is not doing the electrical job regardless of how the section looks.

Plugging is priced by the number of holes, the type and the board thickness, and the increments are large enough to be worth designing around.

The pattern is that the cost step is between Type VI and Type VII, and the reason is the cap. Everything up to Type VI is print, cure and grind; Type VII adds plating, planarising to a tighter tolerance and a second etch compensation. A design that can move a via 0.2 mm and escape it on an inner layer has removed the most expensive line item in the table without touching the electrical requirement.

The role of resin plugging on a high-frequency board is one of three things — stop wicking, remove a cavity, or create a flat land — and the IPC-4761 type has to be chosen to match the role rather than to match the budget. Type II will stop wicking and will not remove a stub. Type V will remove the stub and will not give a printable pad. Type VII will do both and costs the most.

The key considerations reduce to four numbers and one rule. Void content under about 5 %, depression at or below 25 µm, cap plating at the surface thickness, and a CTE mismatch that on PTFE is 80 µm against 17 µm over a reflow excursion — which is a plating and aspect-ratio problem, not a resin problem. The rule is that the type is stated on the drawing, with the depression limit, because an unstated type is a decision made by whoever quotes the job.

XCE PCB fills and caps vias on hydrocarbon, ceramic and PTFE stacks, with 2 to 72 layers, 600×1200 mm panels, impedance ±10 %, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. Send the via table with diameters, depths and the type you need, and the fill will be quoted against the geometry rather than against a category.