Sheet Lamination in PCB Manufacturing: What the Word Means Here

Search for sheet lamination and half the results describe an additive manufacturing process in which metal or paper sheets are bonded and then cut to shape. That is not what a PCB fabricator means by the phrase, and the confusion is not harmless: it produces specifications that ask for the wrong thing. In PCB work, sheet lamination is the pressing of a stack of copper foils, prepregs and cores into one board, and its consequences are dimensional rather than additive — the final dielectric height is the sum of what the sheets became under heat and pressure, and every interface is a place where air can be trapped.

The original article opened with a definition that was correct for PCB work but did not acknowledge the collision, which is why the term is so often mismatched to the wrong expectation. Sheet lamination is a recognised category in additive manufacturing, a recognised step in flexible circuit assembly, and a recognised process in rigid board fabrication, and the three share only the word sheet.

Only the second row is what a rigid-board fabricator means, and it has a defining characteristic that the other two do not: the process is not additive in the design sense. The stack is fully populated before pressing, and the press only changes what the sheets become. Nothing is added, nothing is shaped — thickness, dielectric constant and registration are all outcomes of a single thermal cycle. The sheets being bonded are already patterned, which is why the operation sits downstream of the imaging and etching work described in inner layer circuit fabrication.

A stack is described in sheets because that is how the material arrives and how the press is loaded. Each type contributes a different thing, and each has its own tolerance.

Two rows are routinely underestimated. Bondply is a dielectric as well as an adhesive, and leaving it out of the impedance model takes a 50 Ω line to about 61 Ω when 0.10 mm is unaccounted for — a 22 % error that no press adjustment can recover. And copper foil profile is invisible in every drawing yet decides a large part of conductor loss above 10 GHz, because the current is confined to a skin depth of 0.65 µm and the roughness is comparable to it. The weight-to-thickness conversion and the plated-versus-base difference are set out in copper thicknesses in high-frequency PCBs.

In a multilayer stack the dielectric between two copper layers is not a nominal value chosen from a catalogue; it is whatever the prepreg became after the press. The count and the resin content decide it, and the tolerance accumulates.

The arithmetic of a single interface is simple and the result is not. A 0.254 mm core with two 1080 prepregs becomes 0.254 + 0.06 + 0.06 = 0.374 mm nominal. If the core is ±5 % and each prepreg ±10 %, the worst case is 0.241 + 0.054 + 0.054 = 0.349 mm to 0.267 + 0.066 + 0.066 = 0.399 mm, which is 0.374 ±0.025 mm — ±6.7 %. By the rule that impedance moves with the logarithm of height, that is roughly ±4 % of 50 Ω before any etch variation is counted. The tolerance budget is therefore spent on the stack before the etcher sees the board.

Two practical consequences. First, if impedance is a requirement, the stack should be specified as a pressed height with a tolerance, not as a list of sheet thicknesses — the fabricator has to adjust the count to hit the number, and the drawing should give them that freedom. Second, more sheets is not more accurate: three 1080s are not equivalent to one 7628 plus one 106 mechanically, and the resin content of the thinner sheets means more flow and a greater chance of a resin-starved edge on a large panel. The stack is a compromise between electrical height and process robustness, and the second is what decides yield.

A laminated board contains as many potential void sites as it has interfaces. The number grows quickly: an eight-layer board built from four cores requires three prepreg groups and at least two press cycles, so the interfaces at the outer bond lines see two thermal histories and the inner ones see one.

A void is not cosmetic. Air has a Dk of about 1.0 against 3.4 for the laminate, so a thin layer of it in series with the dielectric lowers the effective Dk and raises the impedance. A 10 µm void across a 0.254 mm dielectric takes the effective Dk from 3.48 to 3.31, about −9.5 %, and moves a 50 Ω line to roughly 52.3 Ω; 50 µm takes it to about 60 Ω. Because the void is local, the coupon can average out to a pass while one trace on the panel is out of specification, which is why void inspection is done by area coverage rather than by a single measured point.

Vacuum lamination removes most of the air present at the start of the cycle, which is why it is standard on high-frequency work, but it does not remove air generated during cure from moisture absorbed in the prepreg. That is why prepreg is stored at controlled humidity and why a press cycle that is too fast produces voids even in a vacuum press: the resin gels before the vapour can migrate to the edge. The article on lamination in high-frequency PCB manufacturing covers the height side of the same process; this page stays with the sheet accounting.

The original article described heating, pressing and cooling without a single value. The window is not wide, and every entry in it exists because something fails outside it.

The reason the last row belongs in a table about sheets is that it decides the order of operations. FR-4 cures at 170–190 °C, RO4000 at 190–200 °C, and a PTFE stack with FEP needs 260–300 °C. Those are three different cycles, so a mixed board cannot be pressed in one operation: the PTFE sub-assembly is laminated first at its own temperature, then bonded to the FR-4 section with a lower-temperature film. The sheet count is therefore fixed by the press sequence, not the other way round, and the delivery schedule follows from the sequence.

On flexible and rigid-flex boards the phrase also describes a separate operation: bonding a coverlay film over a finished circuit to protect it. It is worth separating because the failure modes are entirely different from rigid lamination.

A coverlay is a polymer film with an adhesive layer, opened by routing or laser to expose the pads. The registration of those openings to the pads is the dominant tolerance: an opening 0.1 mm off centre on a 0.3 mm pad leaves an exposed crescent that will wick solder and a covered crescent that will not, and the resulting joint looks acceptable and is not. The adhesive is also a dielectric sitting on top of the trace, so on a controlled-impedance flex it changes the impedance of the top layer — a parameter that is frequently absent from the flex stack drawing and present in the measurement.

Photoimageable coverlay avoids the routing tolerance entirely because the openings are imaged, at the cost of a different chemistry and a limited thickness range. The choice is analogous to the rigid-board choice between mask-defined and copper-defined pads: one is cheaper, the other holds tolerance on small features.

The original text had the sequence right and three of the mechanisms wrong.

Six items turn a stack into something a press operator can hit:

1. Pressed dielectric height per layer, with tolerance, rather than a list of sheet thicknesses — the count is the fabricator’s adjustment variable. 2. Copper weight per layer and the finished outer copper, since outer layers are plated 20–25 µm thicker than the base foil. 3. The material designation per layer, including the bondply, because an unlisted bondply is an unmodelled dielectric. 4. A symmetric construction around the centre line, stated explicitly, since asymmetry produces warp that no press profile fixes. 5. The press sequence for mixed stacks, with the low-temperature bond called out. 6. Void acceptance criteria in area terms, with the inspection method named.

Item three is the one that most often costs a rework cycle. It is also the item that a design file set should carry, and the checklist for what a fabricator needs in order to quote and build a mixed stack is in outputting high-frequency multilayer mixed-pressure PCB design files, while the practical difficulties of bonding two material systems are set out in mixing Rogers sheets with FR-4.

A prepreg is a partially cured resin system, which means it is a material in a metastable state. It continues to advance at room temperature, and the amount of advancement left when it reaches the press is what decides whether it flows. That is why the sheet has a date code and why the date code matters more than most incoming inspections.

The practical instruction that follows is that prepreg should be treated as a dated process material rather than as stock. A stack built from sheets near the end of their life will press to a different thickness and bond with a lower peel strength than the same stack built from fresh material, and neither effect is visible on the panel until the impedance coupon is measured or the board is thermally cycled. The three items a fabricator needs in order to control this are the material date code on the traveller, the storage history, and the conditioning step before use — all of which belong on the process record rather than on the drawing.

Because the press is a batch process with a long cycle, sheet lamination is the step that converts a design decision into a schedule. Three effects dominate, and none of them appear on a quotation line.

First, the number of press cycles. A four-layer board is one cycle; an eight-layer built from four cores is two; a rigid-flex with a PTFE section is three, because the PTFE sub-assembly has its own temperature. Each cycle adds ramp, dwell and controlled cooling — several hours of press time — plus a registration and inspection step, so layer count raises lead time faster than area does.

Second, the panel yield at lamination. Voids, slip and thickness error are all panel-level rejects, so a stack with more interfaces and a larger area has a lower first-pass yield even when nothing about the circuit changed. That is the arithmetic behind a price step at a given layer count.

Third, the irreversible nature of the step. Everything before lamination can be reworked or re-etched; a stack that is pressed with a void cannot be opened. That is why the inspection point immediately after lamination — thickness, registration, and void check — is the last cheap decision on the whole route, and why the panel accounting for substrate cutting has to be right before the press, not after it.

The phrase sheet lamination names three unrelated processes. In rigid PCB work it means pressing a stack of copper foil, prepreg and copper-clad core into one board, and its defining property is that nothing is added: the press decides what the sheets become. Dielectric height is an accounting result — a 0.254 mm core with two 1080 prepregs is 0.374 mm nominal and about ±6.7 % in the worst case, which is roughly ±4 % of impedance before etching is counted.

The interfaces are where the risk sits. Air at a Dk of 1.0 in series with 3.4 raises impedance: 10 µm takes a 50 Ω line to about 52 Ω and 50 µm to about 60 Ω, locally, so a coupon can pass while a trace fails. Vacuum below 50 mbar, a ramp of 2–3 °C/min, 200–400 psi and cooling at 3 °C/min are the numbers that keep that under control, and PTFE at 260–300 °C is the reason mixed stacks cannot share one cycle.

The correction that matters most is the thermal one: lamination does not conduct heat away, it is the thermal resistance. 0.254 mm of a 3.4-Dk material is equivalent to about 142 mm of copper, and a low-loss RF laminate is worse rather than better. XCE PCB laminates mixed stacks with sequenced press cycles on 2 to 72 layers, panels to 600×1200 mm, impedance ±10 %, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015, with void acceptance reported by area rather than by sample. The stack design that these sheets have to realise is covered in high frequency PCB stack-up design.