Performance of High-Frequency PCB: Eight Metrics Converted into Comparable Numbers

Anyone comparing the performance of high frequency pcb materials is handed a table of dielectric constants and dissipation factors and told that lower is better. That table cannot be compared across its own columns: Df is dimensionless, thermal conductivity is W/m·K, Z-axis CTE is ppm/°C, copper roughness is micrometres of profile, and the number a link actually cares about — decibels per inch — appears nowhere.

This article converts the eight properties most often listed for high-frequency laminates into units that can be put side by side, and shows the arithmetic that does the converting. Once the metrics share a unit, three things become visible: which property dominates at which frequency, how much of a measured loss figure is material and how much is copper, and which of the eight is really a manufacturing number rather than a material one.

The usual list runs: dielectric constant, dissipation factor, dielectric thickness uniformity, signal integrity, thermal stability, impedance control, mechanical strength, surface finish. Written that way, seven of the eight are unquantified and the eighth is a category rather than a metric. Split them by owner and by unit and the list becomes usable, because a property that belongs to the laminate cannot be fixed by the designer, and a property that belongs to the process cannot be fixed by buying a more expensive material.

The commercial consequence is immediate. Five of these eight belong to the laminate and are bought; two belong to the fabricator and are negotiated as tolerances; one — roughness plus finish, which together form the conductor loss — sits across the boundary and is usually where a specification quietly fails, because each side assumes the other measured it.

Dk is a dimensional property. Its job is to set how much electrical length fits into a physical millimetre, and through that to set phase, delay and the size of every passive. It does not rank materials by loss, and the two are routinely confused because both appear in the same datasheet column block.

Two readings follow. The first is that moving from 2.20 to 11.20 doubles the phase per millimetre and halves the footprint, which is the entire economic case for high-Dk material in a phased array: the same aperture holds twice the elements. The second is that phase tolerance becomes a different problem on each material. A 1 mm length error is 16° on 5880 and 33° on 3010, so the mechanical tolerance that is acceptable on one is a beam-pointing error on the other. Where that ratio lands in practice is set by the stack, which is why the width and dielectric height have to be fixed before the material is chosen — the arithmetic is in high-frequency PCB stack-up design.

Df is a ratio of energies and cannot be used for a loss budget until it becomes decibels. The conversion for dielectric loss is close to α_d ≈ 2.6 · f_GHz · √Dk · Df decibels per inch. It is an approximation, but it is accurate enough to rank materials and to catch a datasheet comparison that has been made on Df alone.

The fourth row is the reason this conversion matters. RO3010 has a lower Df than RO4350B and a higher dielectric loss, because the √Dk term is 3.35 against 1.91: at 10 GHz that is 0.19 against 0.18 dB/in. The difference is small, but the direction is the opposite of what a Df-only comparison predicts, and the same trap sits behind most “high Dk costs loss” claims. The correct statement is narrower: within one Dk family, lower Df means lower loss per inch; across families, the unit matters more than the ratio. The 4003C against 3003 comparison is a case where the same conversion gives the intuitive answer, and it is worth reading the two side by side in 4003C versus 3003.

Two caveats keep the formula honest. It assumes a homogeneous dielectric, so it describes stripline well and a microstrip only approximately, because half the field is in air and the effective Df is lower than the laminate value. And it says nothing about copper, which at these loss levels is no longer a rounding term.

Measured insertion loss on a 50 Ω microstrip with 1 oz copper at 10 GHz splits as follows. The copper term is remarkably constant — roughly 0.19 to 0.20 dB/in across all four materials — while the dielectric term spans a factor of thirty. The total therefore stops improving once the dielectric term drops below the copper floor.

Notice that the last two rows are 4× apart in Df and only 45 % apart in total loss. On 5880, 84 % of the loss is conductor loss; on FR-4, 84 % of it is dielectric loss. This is the single most useful split in the whole table, because it tells you where the next improvement has to come from: on FR-4, change material; on 5880, change copper. Foil roughness is the lever there, and it is worth about 0.1 dB/in at 10 GHz for a standard profile against a low-profile foil. The copper weight arithmetic behind that term is in copper thickness in high-frequency PCBs, and it is worth remembering that at 10 GHz the current occupies the outer 0.65 µm of a 35 µm foil, so most of the copper is structural rather than electrical.

Most Rogers datasheets publish two Dk values and most designs use only one of them, usually the wrong one. The processed value is measured on a finished laminate with a clamped stripline fixture at a stated frequency; the design value is a fit intended for impedance modelling over a band, typically 8–40 GHz. They differ by up to 10 %, and the difference translates straight into ohms.

A 1.2 Ω systematic offset sounds harmless until it is placed against the tolerance stack in the next section, where the whole budget is often ±5 Ω. Mixing the two values consumes a quarter of the budget before any manufacturing variation exists, and it does so in one direction, so it cannot be averaged out over a panel. The rule that avoids it: the design value goes into the field solver, the process value goes into the acceptance coupon, and the drawing states which is which. The full family table, including the 3210 tolerance of ±0.50, is in the RO3000 series.

Dielectric height is the only variable in the impedance equation that the fabricator sets after the design is frozen, and it is set by a stack of two things: the core, whose thickness carries a laminate tolerance, and the prepreg or bondply, whose pressed thickness depends on resin flow. A 0.254 mm design is often a 0.203 mm core plus 0.05 mm of pressed bondply, and only the first of those two numbers is on the purchase order.

Converted into impedance, a ±10 % height window is worth about ±6 % of Z₀ — roughly 47 to 53 Ω on a 50 Ω target. That single term is larger than every other contributor combined, which is why thickness is the first thing to tighten and the last thing buyers ask about. Two material behaviours make it worse on high-frequency laminates rather than better. PTFE cold-flows: a 4 % compression during lamination moves 50 Ω to 48.8 Ω and does not recover, so the starting thickness has to be ordered above nominal. And on thin cores the process Dk itself changes: 0.101 mm RO4350B is specified at 3.36 rather than 3.48, which is a further 3.5 % and is usually buried in a datasheet footnote.

None of this is visible on a single coupon, which is why the acceptance measurement has to be defined by position. Coupons at the panel centre and at the edge, on every layer that carries a controlled line, and the same coupon geometry used at design time — the sequence that produces those coupons is described in high-frequency PCB design steps, and the layer-by-layer thickness budget sits in PCB structural layers.

“Impedance ±10 %” is a specification of the outcome, not of the process. The outcome is the root sum square of four independent contributions, and on a 0.254 mm stack with a 0.59 mm line they are large enough that the sum lands close to the whole window before anything goes wrong.

Two features of that table are worth carrying into a purchase order. The mask term is signed: it always lowers impedance, because the coating adds capacitance, so a bare coupon that measures 51 Ω will run at 49–50 Ω after masking. And the etch term is a fixed number of micrometres, so its share doubles on thin dielectrics: ±25 µm is 2.8 % of a 0.59 mm line on 0.254 mm laminate, but 5.5 % on 0.127 mm laminate where the line is half as wide. That is the same mechanism, described from the etcher’s side, in photolithography and etching.

A conductivity in W/m·K is only half of a thermal answer; the other half is how far the heat has to travel through it. Thermal resistance per unit area is thickness divided by conductivity, R″ = t/k, and it is that number — not k — that sets the temperature rise of a dissipating line or a hot component pad.

The spread is 7× between 5880 and 6035HTC at the same thickness, and it is entirely a material choice — no amount of copper on the surface changes it, because the heat still has to cross the dielectric to reach a plane. For scale: 0.254 mm of 5880 has the same thermal resistance as 142 mm of copper. That is why “add a ground plane” is not a thermal fix on PTFE, and why the honest thermal options are thermal vias through the dielectric, a metal backing, or a laminate with real filler loading such as 6035HTC.

Of the eight properties, Z-axis CTE is the one most often quoted in the wrong direction. It is not a dielectric-quality number and it cannot be brought close to copper on a PTFE laminate; it is a mechanical load applied to every plated barrel, and the only question is how many micrometres of it the plating has to absorb.

An 82 µm stretch over a 1.6 mm span is roughly three times the wall thickness of a typical 0.3 mm drill, so the plating has to accommodate it as strain rather than as movement. Three rules follow, and they are the ones that keep PTFE boards from failing in the third reflow: plating elongation of at least 20 % rather than the 12–15 % typical of standard chemistries, an aspect ratio of 6:1 or less on PTFE, and reflow cycles treated as a finite resource rather than a repeatable step. The counterintuitive part is that 5880 handles this better than its CTE suggests, because its high expansion is matched by a low modulus — the strain, not the displacement, is what breaks barrels.

Temperature coefficient of Dk is the property that decides whether a board still works at the end of its temperature range, and it is absent from most comparison tables because it does not appear in the marketing abbreviation of a material. The values are not small and they do not share a sign: RO4003C is +40 ppm/°C, RO4350B +50, RO6035HTC −66, RT/duroid 5880 −125, RT/duroid 6010.2LM −425.

Converted to phase on a 100 mm line at 10 GHz, a 200 K excursion moves the electrical length by about 11° on RO4350B and about 22° on 5880. The two are not equivalent, but they are the same order, and both are large compared with the 1–2° that a beam-forming array can tolerate before calibration. The practical consequence: a design with a wide temperature range either calibrates on temperature or chooses the flattest TCDk available, and the second option is why 6010.2LM exists despite its −425 figure being the largest in the family — that number is quoted in ppm/°C over a narrow window, not as a linear coefficient over 200 K.

The honest comparison therefore needs three columns that datasheets rarely present together: Dk at 23 °C, TCDk, and the temperature span over which TCDk was measured. A material with a large coefficient quoted over ±25 K can outperform one with a small coefficient quoted over 200 K inside a narrow window, and lose outside it.

The finish contributes to loss through the same skin-depth mechanism as the copper, and its weight depends on which metal the current actually travels in. At 10 GHz the skin depth is 0.65 µm in copper, 1.33 µm in nickel, 0.63 µm in silver and 0.78 µm in gold. An ENIG deposit of 3–6 µm of nickel is therefore several skin depths thick, and the current in those regions runs in nickel at about 2 times the resistivity of copper; the 0.05–0.10 µm of gold on top is an eighth of a skin depth and carries almost nothing.

Measured as added loss, that is roughly 0.1–0.15 dB/in at 10 GHz and 0.2–0.3 dB/in at 28 GHz for an ENIG board compared with the same board without the nickel layer. Immersion silver and OSP avoid the nickel and land within a few percent of bare copper, which is the real reason they are preferred above 10 GHz — not the conductivity of silver, which is only 3 % better than copper. The finishes, their thickness windows and the qualification standards are set out in PCB surface treatment processes.

Four mechanical figures belong in a performance discussion because they fail boards in production rather than in simulation. Peel strength sets how much handling and thermal cycling the copper can take: RO4003C is specified at 1.05 N/mm and RO4350B at 0.88 N/mm, against 5.5 N/mm for RT/duroid 5880 with 1 oz ED foil and 3.04 N/mm for TLY-5. The PTFE numbers are higher because the foil is bonded through the polymer rather than to a rigid resin, which is also why they behave differently under rework.

Dimensional stability decides registration, and it scales with panel size: over a 600 mm panel and a 20 °C swing, TLY-5 moves 0.31 mm and 5880 0.37 mm, against 0.12 mm for RO4350B and 0.19 mm for FR-4. That is 4–6 % of the registration budget per degree of shop-floor temperature, which is why high-frequency shops measure at 20 ±2 °C.

Flexural modulus decides whether a thin panel survives handling — PTFE laminates are soft enough to drape, which is an advantage in 3D-shaped antennas and a hazard in an automated line. And flammability rating is not a mechanical property but belongs in the same compliance column: RO4003C carries no UL 94 rating at all, while RO4350B is V-0. A substitution between the two that looks electrically acceptable can therefore remove a certification.

Seven of the eight properties are either material data or geometry. The eighth — power delivery impedance — is a property of the assembled structure and cannot be predicted from a datasheet at all. It is a frequency-domain specification: the impedance between the power and ground planes, as seen from the load, has to stay below a target across the band where the current transients live.

The geometric terms that set it are all length ratios. A plane pair resonates when its largest dimension approaches a half wavelength, so a 100 mm board with Dk 3.38 starts to look inductive well below 1 GHz. Ground via spacing has to be small against a quarter wavelength: at 10 GHz in Dk 3.38 a quarter wavelength is 4.1 mm, so the common 5 mm stitching pitch is already past the useful limit, and at 28 GHz it is 1.45 mm. Above roughly 1 GHz the discrete capacitors stop mattering, because their mounting inductance — about 1 nH per millimetre of via and trace — dominates their capacitance, and the plane pair is the only decoupling left. The spacing rules that make this measurable in layout are the same ones covered in trace width and spacing.

Performance is eight numbers with three owners and eight different units. Converting them makes the trade-offs visible: Df becomes 1.08 dB/in on FR-4 against 0.035 on 5880, but total loss only moves from 1.28 to 0.22 dB/in because the copper term is fixed at about 0.19; thermal conductivity becomes a 37 K rise on 4350B against 127 K on 5880 at the same 0.254 mm; Z-axis CTE becomes 11 µm of expansion on 4350B against 82 µm on 5880 over a reflow; and the ±10 % impedance window turns out to be almost entirely consumed by dielectric thickness tolerance before etching is considered.

That is a more useful specification than a ranked list of materials, because each figure names the lever that moves it: thickness for impedance, foil for conductor loss, filler loading for heat, plating ductility for via life, and finish chemistry for the last tenth of a decibel. XCE PCB builds to those windows on 2–72 layers, panels to 600×1200 mm, impedance held to ±10 %, samples in as fast as 24 hours, in a 5,000 m² plant with 80+ engineers and production since 2009, inspected to IPC-A-600G and IPC-6015. What the measurement side of this page looks like — coupons, TDR resolution and where a VNA stops being able to see a defect — is set out in testing in high-frequency PCB production.