Introduction and Function of Single-Sided and Multi-Layer PCBs: What the Extra Layers Buy

The standard introduction and function of single-sided and multi-layer PCBs is written as a list of adjectives: single-sided is cheap and simple, multi-layer is dense and has good signal integrity. None of that explains why the second board costs three times as much, and one of those adjectives is wrong in a way that misleads design teams. The function a multi-layer board adds is not more routing, and certainly not a layer count. It is a reference plane: a continuous return path a fixed distance from every signal. Everything else — impedance you can control, crosstalk you can predict, radiation you can suppress — follows from that one geometric fact. This article defines both boards by what they can and cannot do, then gives the criterion that decides between them: edge length against trace length, not frequency against a spec sheet.

A single-sided board has one copper layer on one face, a dielectric beneath it, and holes that are mechanical rather than plated. A multi-layer board has three or more conductor layers separated by dielectric and joined by plated vias. Those are the definitions, and they are settled. What is not settled in most introductions is the function question: what does the second, third and fourth layer actually do that the first one cannot?

Three things, and only the first one is electrical:

The electrical column is the one that decides most designs, and it is the one usually described in the wrong direction. Multi-layer boards do not have better signal integrity because they have more layers. They have better signal integrity because one of those layers is a plane, and a plane turns an uncontrolled wire into a transmission line with a defined impedance and a return path of known width.

Four elements, and the thickness of each is a specification rather than a default.

The structural detail that matters most and is almost never stated: on a single-sided board the component holes are usually not plated. The lead passes through a drilled or punched hole and is soldered on the copper side, so the hole is a mechanical feature with no barrel, no annular ring requirement and no plating thickness — the contrast with a plated barrel is set out in PCB through hole. That is why single-sided boards are so cheap — there is no electroless copper line, no panel plating and no hole-wall inspection in the flow — and it is also why nothing on a single-sided board can be connected from the back.

Etching has the same trapezoid problem as on any other board, and with no plating afterwards it is the only thing setting width. At an etch factor of 1.5, 1 oz foil undercuts about 23 µm per side, so a 0.2 mm drawn line finishes near 0.15 mm at the base. That is why the practical minimum on a single-sided board is about 0.2 mm rather than the 0.1 mm quoted for a plated inner layer, an asymmetry explained in PCB etching.

It cannot control impedance. Characteristic impedance is a property of a conductor and its return reference. With no plane, the “reference” is whatever copper happens to be nearby — a neighbouring trace, a ground track along the edge, a component lead — so the impedance varies from millimetre to millimetre and cannot be designed or measured against a coupon.

It cannot confine the field. On a board with a plane 0.2 mm below the trace, the return current flows directly underneath and the loop area for a 50 mm trace is about 10 mm². On a single-sided board the same trace may have its return 2–5 mm away in the plane of the board, so the loop area is 100–250 mm². Radiated emission scales with loop area, so the difference is 20–28 dB before any discussion of what the traces are doing.

It cannot predict crosstalk. With no plane, the field spreads through the dielectric and through the air on the component side, and it reaches neighbours that a plane would have screened. Measured side-by-side comparisons at the same spacing typically show 10–20 dB more near-end crosstalk on the board without a reference plane, and the number moves with whatever else is routed nearby, which is the real problem: it is not repeatable.

The question “can this run at 100 MHz on a single-sided board” has no answer, because a 100 MHz sine wave and a 100 MHz clock with a 1 ns edge are different electrical objects. What decides whether a trace behaves as a wire or as a transmission line is the ratio of the signal’s rise time to the time it takes to travel the trace.

Propagation delay on an FR-4 microstrip with an effective Dk around 3.3 is about 6.1 ns/m, or 154 ps/inch. The classic threshold is a flight time of half the rise time; conservative design guides use a sixth.

Read the table as a design rule rather than a limit. A single-sided board with a 1 ns driver and 60 mm of trace is at the boundary: it will work in the lab and fail EMC, or work at room temperature and ring at 85 °C when the driver slows. The reason is not that the board is single-sided; it is that the return current has to find a path, and at that edge rate the path it finds is a loop antenna.

Wavelength gives the same answer in the frequency domain. On the same laminate the guided wavelength is 1.65 m at 100 MHz, 165 mm at 1 GHz and 16.5 mm at 10 GHz, so a 50 mm trace is λ/33 at 100 MHz and λ/3 at 1 GHz. Phase, delay and coupling all become layout-dependent somewhere between those two.

Layers are not added one at a time. They are added in pairs, because a stack has to be symmetric to stay flat, and the useful configurations are set by a simple counting rule: a stripline needs a plane above and below, so n stripline layers need at least n+1 planes.

That is why the four-layer board is the first one that is electrically different rather than merely denser: it is the first one where every signal can see a continuous plane. It is also why a two-layer board with a ground pour is not a substitute: the pour is perforated by the very traces it is supposed to reference, and the return current has to detour around every one of those perforations, which is where the loop area in the previous section comes from.

The layer-by-layer construction, and the rule that the stack is derived from the planes rather than from the routing, is set out in PCB layer structure and in high-frequency PCB stack-up design.

Cost is not linear in layer count, and the reason is that each pair of layers adds a press cycle, an inner-layer imaging step, an AOI step and a registration risk.

The table is a ratio, not a price, and it moves with panel utilisation, hole count and material. What it shows is the shape of the decision: going from one layer to four roughly triples the board cost, and going from four to eight roughly doubles it again. A design that adds four layers to save 200 mm² of board area is usually making a bad trade unless the enclosure is the binding constraint.

Yes, within limits that are set by geometry rather than by the word “high frequency”. A coplanar waveguide — a signal trace with ground tracks either side on the same face — gives a defined impedance without a back-side plane, and single-sided CPW filters and antenna feeds are common below about 6 GHz on low-cost substrates.

The costs are specific. The ground tracks have to be wide enough and stitched often enough that they behave as one conductor, and on a single-sided board there is no second face to stitch to, so the “ground” is a set of tracks whose inductance depends on how far apart the stitching points are. Radiation loss rises because the field is not confined to one side of the board, and the effective Dk sits between the substrate and air, which makes the impedance sensitive to conformal coating, enclosure proximity and even humidity.

Above roughly 10 GHz the balance tips: the wavelength on the board is 16.5 mm, a transition or a bend is a measurable discontinuity, and there is no plane to reference the return. At that point the board is not “single-sided high frequency”, it is a mechanical carrier with an antenna on it, and the RF laminate decision has already moved the design to a multilayer stack.

The original article, like most introductions, contains statements that read well and fail on inspection. Five of them:

The flow difference is the reason for the cost difference, and it is a difference in kind rather than in effort.

The practical consequence for a buyer is that a single-sided quote is dominated by material and tooling, while a multi-layer quote is dominated by process steps and yield. That is why the same outline can be quoted at three very different prices by shops with the same material cost: what differs is the number of press cycles they are willing to run and the impedance verification they include. The twelve steps behind that quote are mapped in high-frequency PCB manufacturing process.

Five questions, in this order, settle the choice for most boards:

1. What is the shortest edge in the design, and how long is the longest trace it drives? If the trace is shorter than t_r/2 in flight time — 82 mm at 1 ns — a plane buys little. 2. Does anything need a controlled impedance? If yes, a plane is mandatory and the board is at least four layers. 3. Is there a compliance requirement? Radiated emission limits are usually what forces the plane on an otherwise marginal design. 4. How many nets have to cross each other? Crossovers, not component count, drive the layer count. 5. What does the enclosure allow? A 4-layer board is thicker and heavier than a 1.6 mm single-sided one, and in a handheld product that can be the binding constraint.

Answer those five and the layer count is usually obvious. What is left is the choice within a family — single-layer, multilayer or high-layer-count with blind and buried vias — which is a question of density and via strategy rather than of electrical function, and it is covered in multilayer versus single-layer high-frequency PCBs.

A single-sided board is one copper face with unplated holes; a multi-layer board is three or more conductor layers with plated connections. The function that the extra layers add is a reference plane, and from that plane come controlled impedance, a confined field, predictable crosstalk and measurable coupons. The layer count is a consequence, not the cause: four layers is the first configuration where every signal can see a continuous plane, and eight is where a proper stripline stack becomes economic.

The criterion for choosing between them is measurable and has nothing to do with a frequency printed on a datasheet. Compare the rise time to the flight time: 6.1 ns/m on FR-4 means a 1 ns edge is critical at 82 mm, a 300 ps edge at 25 mm and a 100 ps edge at 8 mm. Below those lengths a plane is a luxury; above them it is the only way to know what the trace impedance is.

XCE PCB builds both ends of that range: single- and double-sided boards for control and power, and high-frequency multilayer stacks from 4 to 72 layers on 600×1200 mm panels, impedance held to ±10 % with coupon verification, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. If the edge-rate calculation lands near a boundary, send the stack and we will quote both — request a quote or WhatsApp +86 180 3818 8537.