Key Production Stages and Considerations for High-Frequency Circuit Boards: Seven Windows That Decide the Board

Most articles on the key production stages of a high-frequency circuit board read as a list of eight stations with a tick and a warning beside each one. That format is easy to write and almost useless to work from, because it never says what number the station is holding, what the window is, or how the error shows up later. A stage list is a route; a control plan is the set of quantities that, once missed, no downstream station can recover. This article is the second kind.

The list most suppliers publish has eight entries: material, imaging, drilling, plating, lamination, mask, finish, test. Read closely, three of them are in the wrong order relative to a real build and none of them carries a number. The reason the list survives is that it is not meant to control anything — it is meant to sound complete.

A control plan does one thing: it names the quantity that each station is responsible for, and treats that quantity as unrecoverable. That last word is what makes the plan useful. Line width can be measured after etching, but it cannot be widened afterwards. Dielectric height is fixed by the press, not by the etcher. A hole wall that was not activated cannot be made to bond by plating harder. When a station is described as “a consideration”, the reader is left to work out for himself which of these it is.

On a high-frequency board, seven quantities carry almost all of the electrical outcome. They are the ones worth writing down, and each one has a signature defect that appears two or three stations later if it drifts.

The stations that follow each of these — solder mask cure, legend, routing, packing — matter for yield, but they cannot move a quantity that has already been frozen. That is the distinction this article works with, and it is why the route map and the control plan should be two different documents. The route map, station by station, is set out in the twelve-step high-frequency PCB manufacturing process; this is the other document.

A laminate certificate of conformity carries a Dk, a Df, a thickness and a lot number. It is a real document and it is worth having, but it answers a narrower question than most buyers assume: it states that the lot is within the manufacturer’s specification at the frequency and method named in the data sheet. It does not state the value that your coupler will measure, because it is not measured on your geometry.

Three things sit outside the certificate. The first is thickness distribution within a panel: a core that is within ±10 % overall can still vary across its area, and the impedance of a 50 Ω line follows local height rather than the nominal. The second is copper foil roughness, which the laminate data sheet does not always name but which dominates conductor loss once dielectric loss has been engineered down. The third is the Dk spread between lots, which is small for PTFE and larger for ceramic-filled hydrocarbon materials.

The practical consequence is that the incoming inspection should measure something the certificate does not. On a high-frequency lot, that means a coupon or a qualification panel measured on the same geometry the production board uses, and a thickness check at several points rather than one. It also means treating a supplier change at the laminate level as a design change, not a purchasing change: the same nominal grade from a second source can be 0.1 in Dk and 0.01 in thickness away, which at 0.254 mm is a different impedance.

Only one thing in this stage is an absolute rule. Material families do not mix in a press cycle, but they do mix in a board. A hybrid stack of FR-4 and a hydrocarbon laminate is standard practice and is what makes a mixed-signal product affordable; what cannot happen is pressing the two in one cycle, because their cure windows are 30 °C apart. The process side of that is in hybrid dielectric PCB technology.

Cutting is treated as a warehouse task and it is the first station that can lose the registration budget. The reason is not saw accuracy, which is 0.1–0.2 mm on a modern shear, but thermal expansion between the temperature at which the panel was measured and the temperature at which it is machined. Over 600 mm and 20 °C, the movement is larger than every other tolerance in the stack combined.

Two considerations follow, and both are control items rather than preferences. Panels should be cut oversize by 3–5 mm and allowed to relax before the final trim, because a PTFE sheet that is sheared and immediately pinned will hold the stress and release it in the press. And PTFE should be cut by shear or router, not by laser: an IR beam hot enough to cut the sheet decomposes the polymer at around 400 °C, releasing hydrogen fluoride and leaving a carbonised edge that will not bond. The window is in substrate cutting for high-frequency PCB.

The single most useful number in this station is not the resolution of the exposure tool; it is the side etch. Acid etching removes copper laterally as well as downward, at a rate set by the etch factor, and the rule of thumb is simple: the loss per side is approximately the copper thickness divided by the etch factor.

With an etch factor of 1.5, one ounce copper (35 µm base, 23 µm per side at the trace edge) loses 23 µm of width on each side. A line drawn at 100 µm therefore finishes at 54 µm at the base, 77 µm on average, and its resistance rises by roughly 30 %. At two ounces the loss is 47 µm per side, and a 100 µm line is etched away entirely — which is why 0.15 mm is the practical floor for heavy copper.

On a 50 Ω line the same absolute error is a much smaller relative error: at 0.56 mm, 23 µm is 4 % of the width and moves the impedance by under 2 %. The reason fine lines are the ones that must be compensated is exactly this asymmetry, and it is why a single blanket compensation value applied to a whole panel is a compromise rather than a control.

The other consideration in this station is registration. A photoplotter with 40 ppm scaling error moves 0.024 mm across 600 mm, which is tolerable against a 0.075 mm layer-to-layer budget but not negligible when combined with press shrinkage. Below 0.075 mm, direct imaging is the practical route rather than a luxury. The etch side of this station is treated in full in inner layer circuit fabrication.

Lamination is where the dielectric height is decided, and dielectric height is the strongest single term in the impedance budget. A ±10 % thickness window is a ±6 % impedance window on a microstrip — that is, the thickness tolerance alone consumes most of a ±10 % impedance specification before etching, Dk spread or plating are counted. Stating the window correctly matters more than the pressure profile.

The consideration that is most often written wrong is temperature. A high-frequency stack is not pressed cool and gentle. There are three press systems and they are not interchangeable: standard FR-4 cures at 170–190 °C, hydrocarbon laminates such as RO4000 bond at 190–200 °C, and PTFE bonded with FEP film requires 260–300 °C. A sentence such as “use low-temperature, low-pressure lamination to protect the dielectric” is not conservative advice; on a PTFE stack it is a recipe for an unbonded panel.

Three further considerations belong to this station rather than to design. Prepreg shrinks 0.02–0.05 % on cure, which is 0.12–0.30 mm across a 600 mm panel and therefore larger than the layer-to-layer registration budget it is competing with. Air trapped under a bondply behaves as a series capacitance with Dk 1.0: a 10 µm void lowers the effective Dk by about 9.5 % locally and pushes a 50 Ω line to roughly 52 Ω, while the panel average still looks correct. And PTFE cold-flows: pressing 4 % out of the dielectric takes a 50 Ω line to 48.8 Ω, and the change does not come back. The full window is in lamination in high-frequency PCB manufacturing.

One line in the original list is backwards: it recommends laser-drilled blind and buried vias as the preferred approach for high-frequency boards. Laser drilling is the right tool for microvias of 0.1 mm and below in an HDI build-up, where the hole is one dielectric layer deep and the bottom pad is copper. It is the wrong tool for a 0.3 mm through hole in a 1.6 mm PTFE stack, and it is impossible for a buried via that spans several laminated layers, because a via that does not reach an outer surface has to be drilled while that surface is still exposed — which means a sequential lamination, not a different drill.

For the mechanical side, PTFE changes the parameters rather than the machine. The polymer is soft and has a low modulus, so the drill tends to push rather than cut; spindle speed is therefore lower than on FR-4, the point geometry is blunter, and the stack height is limited so that swarf can clear.

The consideration that decides whether this stage is under control is not the diameter but the wall. A finished hole is the drill minus twice the plating thickness, so a 0.30 mm finished hole needs a 0.25 mm drill at 25 µm per wall. If the drill wanders, the plating thickness varies, and the aspect ratio that the plating bath actually sees is worse than the drawing says. Desmear is the second half: PTFE cannot be desmeared with permanganate, because there is nothing for the chemistry to attack. It needs sodium naphthalenide or plasma. The drilling side is set out in drilling high-frequency PCB.

PTFE has no polar groups on its surface, which is the property that makes it a good dielectric and a bad substrate for adhesion. Every metallisation route therefore begins with an activation step that either grafts polar species onto the surface (sodium naphthalenide) or physically roughens it in a vacuum (plasma). Neither step is optional and neither can be replaced by a longer etch. When a PTFE board fails at the barrel, the cause is usually in this step rather than in the plating bath.

The plating itself has three numbers worth writing into the plan. Electroless copper runs at 45–50 °C and deposits 2–3 µm per hour, which sets the minimum time for full coverage of a 6:1 hole. Panel plating then has to reach 20–25 µm in the barrel while the surface is at 42 µm or more, because the current density at the hole centre is a fraction of the surface value. And the deposit needs elongation of at least 20 %, because the Z-axis expansion it will see at reflow is large: over a 1.6 mm board and a 215 °C excursion, RT/duroid 5880 expands about 82 µm against roughly 11 µm for RO4350B. The barrel has to stretch, not crack.

The consideration often missed is that this stage is where a thin board is most exposed. Z-strain on 5880 measures about 4.4 %, on TLY-5 about 4.0 %, against 0.30 % on RO4350B. A fabricator who runs the same plating recipe across both families will pass the hydrocarbon boards and fail the PTFE ones, and the failure will appear at the customer’s reflow rather than at final inspection.

Solder mask is specified as a protective coating and behaves as a dielectric. Its Dk is typically 3.5–4.2, which is above every RF laminate in common use, and it sits directly on the outer conductor where the field’s outer edge lives. On a microstrip, a 20–30 µm mask lowers the characteristic impedance by 1–3 Ω depending on line width. That offset is real, it is repeatable, and it is absent from most stack-up models.

The legend is worse, because it is not a coating but an ink with a high pigment loading. White legend measures around Dk 6.5. A legend that crosses a matched line is not a cosmetic defect; it is a local 20 % change in the dielectric constant of the outermost layer, and on a 0.3 mm wide line it is measurable. This is why high-frequency layouts keep legend off the RF traces and why “no legend over RF” belongs in the fabrication notes rather than in a style guide. The keep-out logic is in silk screen on high-frequency PCB.

Two process considerations attach here. Mask must be cured completely, because an undercured mask outgasses in reflow and blisters over a via; and mask must not be used to plug a via that carries a signal, because the plug will not be void-free and the impedance discontinuity is inside the hole where it cannot be inspected.

Surface finish choice is usually argued on solderability and shelf life. On a high-frequency board the argument has to include conductivity, and the controlling number is skin depth: at 10 GHz the current in copper occupies about 0.65 µm, in nickel about 1.33 µm, in gold about 0.78 µm.

The consequence is concrete: an ENIG finish places 3–6 µm of nickel in the current path, and the 0.05–0.10 µm gold above it does not carry the current, because it is thinner than the skin depth by a factor of eight to fifteen. The penalty is about 0.1–0.15 dB/in at 10 GHz and 0.2–0.3 dB/in at 28 GHz. OSP has the lowest loss because it leaves bare copper and a film measured in nanometres; immersion silver is second. Above 20 GHz with a wire-bond requirement, a nickel-free route is the only one that does both jobs. The full comparison is in PCB surface treatment processes.

Routing looks like the least technical station and it holds two of the failures that reach the customer most often: copper burr on the edge and delamination at a cavity wall. A router at the wrong feed rate smears the PTFE instead of cutting it, and the smeared edge is where a crack starts at the first thermal cycle.

The structural consideration that belongs here is the press count. A stack that mixes an FR-4 section with a PTFE section cannot be pressed in one cycle, so it is built as a PTFE sub-assembly bonded at 260–300 °C, then bonded to the FR-4 at 190 °C with a low-flow film. That second cycle is a second chance to lose registration: the sub-assembly shrinks, and the drill programme that was correct before the second press is now 0.1 mm off. The measurement and control side of this is in multilayer lamination for high-frequency PCBs.

Testing is the stage where expectations most often exceed capability. Every method on a high-frequency line has a blind spot, and the blind spot is usually the thing that fails.

The practical conclusion is that acceptance has to be defined as a measurement on a named structure at a named frequency, not as “impedance tested”. A coupon measured with TDR at one frequency confirms geometry; it does not confirm Df, and it does not confirm that the product line has the same geometry as the coupon unless the coupon is placed where the panel is representative. The test methods and their judgement criteria are set out in testing in high-frequency PCB production.

Assembled, the eight stations reduce to the table below. It is short enough to attach to a purchase order and specific enough to argue about, which is what a control plan is for.

One further consideration, which belongs to the plan rather than to any station: the record is what makes the window enforceable. A fabricator who can show the press curve for the lot, the etch factor used and the coupon measurement at the named frequency has a defensible position when a board is questioned; one who can only show a final continuity pass has a conversation.

The key production stages on a high-frequency board are not eight equal steps. They are seven quantities, each locked at one station, each with a window narrow enough to be measured and each unrecoverable once passed. Dk and thickness come in with the material, line width is decided at the etcher, height is decided at the press, hole geometry at the drill, barrel integrity at the plating line, the outer-layer effective Dk at the mask screen, and surface conductivity at the finish.

Read that way, the considerations stop being advice and become numbers: ±10 % on thickness is ±6 % on impedance; 23 µm of side etch is 30 % of a 100 µm line and 1.2 % of a 0.56 mm one; 3–6 µm of nickel is two to five skin depths at 10 GHz; a 10 µm void moves a 50 Ω line by 2 Ω while the panel average stays in specification.

XCE PCB builds high-frequency and microwave boards to a written control plan: 2 to 72 layers, PTFE, hydrocarbon and ceramic laminates, 600×1200 mm panels, impedance ±10 % with coupon data, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. If the window in this article does not match what your drawing asks for, that gap is the first thing worth settling — the quote is quick, and the review is faster than a re-spin.