In-Depth Analysis of Common Scrap Causes and Effective Avoidance Strategies

Scrap on a high-frequency board is not one problem with one cause; it is a price that changes depending on where in the route the defect is discovered. The same 50 µm of misregistration costs one inner-layer core at AOI and costs the entire accumulated value of a PTFE multilayer at final test — the material, the press cycles, the drilling, the plating, the finish and the labour on every panel in the lot. This in-depth analysis of common scrap causes therefore starts with the economics of detection, then works through each station with the mechanism, the number that governs it and the control that actually prevents it. Several of the causes usually blamed are not causes at all, and one of them — PTFE moisture absorption — is the opposite of the truth.

Two boards with the same defect can differ in cost by a factor of ten. A 50 µm registration error found at inner-layer AOI scraps a single core; found after lamination it scraps the core plus the bondply plus the press cycle; found at final electrical test it scraps all of that plus drilling, plating, soldering mask, surface finish and the electrical test time itself. On a 5880 multilayer the laminate alone can be twenty times the cost of the same area of FR-4, so the multiplier applies to a much larger base.

The operational conclusion is uncomfortable but simple: the cheapest yield improvement on high-frequency work is not a better process, it is an earlier measurement. Every control that moves a discovery one station upstream removes a multiple from the cost of the defect it catches. That is why the test plan belongs in the stack review and not in the shipping department.

The distribution is not even across the route. Five stations account for most of it, and each one has a different signature: a mechanism, a measurement that reveals it, and a control that prevents it.

The most common attribution error in high-frequency scrap is moisture. PTFE is routinely described as hygroscopic and it is the least hygroscopic laminate in the building: 0.02 % by weight for RT/duroid 5880, against 0.05–0.06 % for RO4000 and 0.1–0.2 % for FR-4. A PTFE core left in a humid store does not pick up enough water to blister.

What PTFE does suffer from is contamination and cold flow. Its surface energy is so low that dust does not adhere electrically but does adhere mechanically, and a single particle between layers creates a 20–50 µm tent in the bondply that becomes a void. And it deforms plastically: a press cycle at 200 psi can thin a core by 4 %, which on a 0.254 mm dielectric moves 50.0 Ω to 48.8 Ω and never recovers. Neither of those is a storage problem in the humidity sense, and neither is fixed by a desiccant cabinet.

The storage rules that do matter are unglamorous: 23±2 °C, 40±5 % RH, first-in-first-out, vacuum sealing after opening with the date written on the bag, and a separate bake profile per family — because one bake for a mixed stack either under-dries the FR-4 or over-exposes the PTFE to thermal history it does not need. The material-handling side of the same question is covered in the difficulties of manufacturing Rogers boards.

A category of scrap never appears on a Pareto chart because it is discovered at the customer, not at the factory: the board was built correctly to the wrong material. Four versions of it recur.

The process route is wrong for the family. A stack specified as “Rogers” without a grade may be quoted on the thermoset route and delivered in a ceramic-filled PTFE, or the reverse. The electrical result can be close and the reliability result is not: PTFE needs sodium naphthalene and 260–300 °C fusion, and a shop that treats it as FR-4 produces hole walls that pass backlight and fail thermal cycling. The design Dk is used as the process Dk. RO4003C is 3.38 as a process value and 3.55 as a design value; a stack computed on 3.38 and built with a design model on 3.55 lands about 2 % off on impedance before any manufacturing error. A compliance attribute is lost in substitution. RO4003C has no UL 94 rating while RO4350B is V-0; swapping one for the other on price removes a qualification that had nothing to do with price. The nominal thickness is treated as the dielectric height. The number on the laminate datasheet is the core, and the height that determines impedance is the core plus the pressed bondply — forgetting a 0.10 mm bondply moves 0.56 mm from 50.0 to 61.1 Ω, a 22 % error that no process control can recover.

All four are caught by one document: a stack drawing that names the grade, states process and design Dk separately, records the compliance attributes and lists every bondply with its pressed thickness. The comparison logic for the most commonly confused pair is in choosing between 4350B and 4003C.

Etch is where the first manufacturable error enters, and its size is set by physics rather than by skill. The etchant attacks downwards and sideways at the same time, so the finished trace is a trapezoid whose top is the artwork width and whose base is narrower by twice the lateral attack. The lateral attack is approximately the copper thickness divided by the etch factor.

Two conclusions follow. Fine lines on thick copper is a contradiction, not a process choice — which is why 0.10 mm geometry is normally built on 0.5 oz. And the compensation an etcher applies is roughly one copper thickness, meaning the artwork must be drawn wider than the finished line, and the drawing must say which of the two numbers it is quoting. A board that is 14 % narrow on a 0.10 mm line is 7 % off on impedance; the same absolute error on a 0.56 mm line is 1.2 % and invisible. The full etch treatment is in inner layer circuit fabrication.

Lamination scraps boards for three reasons that are often reported as one. Thickness is a predictable error that should have been modelled; voids are a contamination and outgassing problem; registration is an accumulation problem.

The void row is the one that surprises people, because it explains a failure that looks like a mystery: a lot in which the average impedance is in specification while one trace on one board is 4 % high. A void is a series air layer of Dk 1.0 in the middle of the dielectric, and its effect is local. Average-based acceptance cannot see it; a per-trace TDR coupon on a representative panel can. The press side of this is in lamination in high-frequency PCB manufacturing.

Registration is the only defect on this list whose size grows with the number of process steps rather than with the difficulty of one. Each lamination adds roughly ±25 µm of positional error, each drill adds its own, and each subsequent imaging step adds another. A four-layer board with one press is not the same problem as a twelve-layer hybrid with three.

The budget is easiest to see on a microvia. A 100 µm via landing on a 250 µm pad has 75 µm of annular ring on each side if everything is perfect. Two press cycles at ±25 µm consume two thirds of that before drill wander, material movement and image distortion are counted. That is why stacked vias carry a yield penalty against staggered vias and why a design that can use a staggered structure should: the same connectivity, one less accumulated error.

Control is procedural: four-slot pinning rather than two, X-ray of the first board of every lamination batch, a parallelism check on the press platens, and a drill file organised by span rather than by layer number, because the span is decided by the press order. A registration error that reaches final test is not a registration problem any more; it is a scrap problem at fifteen times the cost.

Hole-wall defects are the most expensive scrap on the list because they are the least visible at the time they are made. A barrel with 60 % copper coverage passes a continuity test, ships, and fails after three thermal cycles at the customer. Three mechanisms dominate.

Smear. Drilling generates enough local heat to soften the resin, which smears across the copper of the inner layer and creates an intermittent connection. On PTFE the window is narrow: 80–120 krpm, point angle 130–140°, helix 35–45°, and no more than three panels in the stack. Adhesion. PTFE is non-polar, so permanganate desmear that works on epoxy leaves it untouched; sodium naphthalene or plasma is required, and the two differ in uniformity. A hole that passes backlight but has no chemical bond will pull out under thermal stress. Barrel strain. With a Z-CTE of 237 ppm/°C against copper’s 17, a 1.6 mm board stretches the barrel by about 82 µm over a 215 K excursion. That demands plating elongation of at least 20 % and an aspect ratio at or below 6:1, or the crack starts at the corner where the strain concentrates.

For acceptance, the useful criteria are quantitative: copper coverage in the barrel, minimum barrel thickness to IPC-6012 for the class ordered, and a thermal stress test that actually reproduces the excursion. Backlight is a screening tool with a graded scale, not a specification, and treating one grade as a pass mark without a cross-section to back it up is how a latent defect gets shipped. The drilling side is in drilling in high-frequency PCB manufacturing, the plating side in electroless copper plating.

Solder mask is treated as decoration and it is an electrical layer. Its Dk is roughly 3.5–4.2 and the legend ink is worse, near 6.5, so a 25 µm coating over a microstrip pulls the impedance down by 1–3 Ω — between 2 and 6 % of a 50 Ω target. Designs that open the mask over the RF trace do so for that reason, at the cost of solder dams and assembly risk.

On PTFE the problem inverts: the mask will not stick to a surface with a surface energy that low, and the fix is the same activation that the copper needs. Mask peeling at the edge of a cavity or a via is a scrap cause that appears only after reflow, because the thermal excursion is what lifts an adhesion that was marginal at room temperature. Two controls matter and both are cheap: measure mask thickness over the RF traces rather than over the laminate, and pull-test the ink on a PTFE coupon from the same lot. The mask process is set out in solder mask application.

Two finish-related scrap modes dominate, and one widely repeated explanation for a finish choice is wrong.

Black pad. In an ENIG bath the phosphorus content of the nickel deposit must stay in a 7–10 wt % window. If it drifts high and the bath is aged, the nickel surface becomes phosphorus-rich — 20–30 at % at the extreme — and the gold will not bond to it. The joint fails at the Ni/Ni₃Sn₄ interface, often only after thermal cycling, which is why it escapes incoming inspection. The controls are the phosphorus window, a gold thickness cap of 0.10 µm, an IPC-4552B corrosion rating written into the purchase order, and bath age managed by metal turnover rather than by calendar.

Nickel loss at millimetre wave. At 10 GHz the skin depth in copper is 0.65 µm and in nickel 1.33 µm. An ENIG deposit is 3–6 µm of nickel under 0.05–0.10 µm of gold, so the current is running almost entirely in nickel, whose surface resistance is about twice that of copper. That is worth roughly 0.1–0.15 dB/in at 10 GHz and 0.2–0.3 dB/in at 28 GHz.

This explains the myth. Immersion silver is preferred for millimetre-wave loss not because silver conducts better — it is only about 3 % better than copper — but because it puts no nickel between the copper and the air. The decision is about the absence of a layer, not the presence of a metal. The complete comparison of finishes is in PCB surface treatment processes.

Every control above is a measurement, and the cheapest place to buy a measurement is before the lot is built. A test plan that costs a few coupons per lot routinely removes more scrap than a process upgrade, because it converts a failure into an adjustment.

Four measurements cover most of the exposure: a coupon TDR per impedance layer, measured at a stated frequency band; a microsection at first article covering hole wall, plating thickness and registration; an ionic contamination check after plating and before mask; and a thermal stress or thermal cycling sample on a periodic basis rather than per lot. Each one is cheap; each one catches a different class of defect that no other test can see.

The discipline that makes them work is that the numbers must be written into the purchase order before the lot starts, not negotiated after it fails. A coupon with no specified geometry measures whatever the etcher felt like building; a microsection with no specified locations inspects the easiest place to cut. What each stage can and cannot prove is set out in high-frequency PCB testing.

Most scrap reviews fail because they start with the defect and not with the population. Five questions, asked in this order, find the cause faster than any amount of microscope work.

1. Is it one board, one panel, one lot or one design? A single board is handling; a panel is a station; a lot is a material or a bath; a design is a rule that is being violated systematically. 2. Did it appear at the same location on every panel? Same location points to tooling or artwork; random location points to contamination. 3. Is the defect the same for every material family, or only for PTFE? If only for PTFE, suspect activation and cold flow before suspecting the operator. 4. What was the last thing that changed? Laminate batch, prepreg lot, drill bit lot, bath turnover, a new operator, a new stack revision — one of those, and usually the one nobody documented. 5. Was the defect detectable at an earlier station, and if not, why not? This question is what turns a scrap report into a test-plan improvement, and it is the only one that reduces the cost of the next occurrence.

Answering them takes an hour and needs no equipment. What it needs is the discipline to record the panel position, the material batch and the station history on every scrap, which is why digital traceability is worth more on high-frequency work than on FR-4: the material cost per panel is high enough that a single avoided lot pays for the system.

Scrap on high-frequency boards is concentrated, priced by detection point and only partly physical. The physical part — etch undercut, thickness deviation, void, registration, barrel strain, phosphorus drift — is predictable and each item has a number that governs it. The economic part is that the same defect costs 2–3 times at AOI and 15–20 times at final test, so moving a measurement upstream is worth more than moving a process window.

Two attributions are worth retiring. PTFE does not absorb enough water to blister anything at 0.02 %; the moisture that does the damage is in the prepreg, the bondply and the FR-4 layers of a hybrid. And immersion silver is not a better conductor in any meaningful sense — it is a finish without nickel, which is the whole point at 28 GHz.

XCE PCB runs 2 to 72 layers on PTFE, hydrocarbon and ceramic laminates, panels to 600×1200 mm, impedance ±10 % verified on coupons, samples in as fast as 24 hours, to IPC-A-600G and IPC-6015. If a lot has scrapped and the cause is still open, send the Pareto and the panel map; the twelve stations above usually narrow it to two candidates. The station-by-station map of the whole route is in high-frequency PCB manufacturing process.