Key Points in High-Frequency PCB Design: Twelve Review Checks With a Number on Each

The key points in high frequency PCB design are usually delivered as a list of good intentions — choose stable materials, control impedance, keep traces short, use enough ground. None of those sentences can be signed off, because none of them carries a threshold: a reviewer cannot say whether the design passes. This article keeps the twelve subjects that matter and converts each into a check with a number, the calculation behind the number, and the specific case in which the rule is wrong and must be overridden.

A design review is a sequence of decisions that can be audited. “Keep high-frequency traces short” cannot be audited; “no single-ended trace exceeds 18 mm at 10 GHz without a controlled stack” can. The difference is not pedantry, it is the difference between a checklist that catches a mistake in layout and one that catches it after the first article fails test.

Twelve checks cover the ground that the eight headings of the original article tried to cover: loss budget, impedance, stack-up, line width, spacing, bend and length matching, return path, power delivery, vias, decoupling, thermal, and testability. Each one below gives the governing number, the formula or table it comes from, and the one situation in which following the rule makes the board worse. A check that never has an exception has not been thought through.

The order is deliberate: the first four checks are decided on paper and are irreversible once the stack is released; the rest are decided in layout and can be revised. A review that spends its time on bend angles while the stack was never checked has optimised the wrong end of the process. The broader decision sequence is in how to design a high-frequency PCB, and the seven-step workflow in high-frequency PCB design steps; this article is the audit sheet that sits on top of both.

Material selection is a loss-budget decision expressed as a distance. The dielectric attenuation of a 50 Ω line is close to αd ≈ 2.6 · f_GHz · √Dk · Df in dB per inch, so what the customer is actually buying is how far a signal travels before it loses 3 dB. At 10 GHz, with 1 oz copper included, that distance separates the families by a factor of five.

Two checks follow from the table. First, the required distance is measured on the longest net, not the average: a 60 mm link on FR-4 has spent the whole budget before the connector is reached. Second, Dk and Df are independent decisions. Choosing a high-Dk material such as RO3010 (Dk 10.2, Df 0.0022) shrinks the circuit because λg falls, but it does not lower loss — over the same electrical length the dielectric loss is set by Df alone, and 3010 is 10 % worse than RO3006, not better. The check to write on the drawing is a pair of numbers: Df ≤ a stated value at the highest operating frequency, and Dk within a stated tolerance, because the tolerance, not the nominal value, sets the impedance spread.

The exception: below roughly 2 GHz the copper is the larger term. On a 0.254 mm stack at 2.5 GHz, dielectric and conductor loss are within 20 % of each other, so moving from 4350B to a 0.0010 laminate buys almost nothing while widening the trace (thicker dielectric) buys a measurable amount. Material upgrades pay where the electrical length is long and the frequency high — not where a datasheet looks better.

±10 % is the standard window offered by fabricators, and it is consumed by four independent contributions before the TDR is connected. Writing the budget down at design time is the only way to know whether the request is possible.

The dominant term belongs to the fabricator, so the useful design-side action is to stop spending the remaining budget twice. Three habits do the damage: designing the line width to the nominal stack and never re-checking after the fabricator adjusts a prepreg; forgetting the bondply, which on a mixed stack adds 0.10 mm of Dk 3.5 and turns a 50.0 Ω line into 61.1 Ω (+22 %); and specifying an impedance window tighter than the stack can hold, which is how ±3 % requests become schedule problems rather than electrical ones.

The exception: on a stripline the same ±25 µm etch tolerance costs twice as much impedance, because a buried line is about 2.5 times narrower than a microstrip of the same impedance (0.226 mm against 0.56 mm on a 0.254 mm dielectric). Isolation is bought with tolerance sensitivity. Where the design needs both tight impedance and buried routing, the answer is a thicker dielectric, not a tighter callout.

The design side of this arithmetic, including layer types and their tolerance penalties, is set out in common impedance designs and layer stacks.

Layer count is an output, not an input. Every stripline needs a reference plane above and below, so a stack that carries n stripline signal layers needs at least n+1 planes. That single sentence kills two popular statements: that a four-layer board can host stripline (it cannot — two planes leave room for two signal layers, and only one of them is buried between planes if the outer layers are also used), and that eight layers always means four signal and four ground.

The check to apply: every signal layer must have an adjacent continuous plane, and no trace may cross a plane split. The second half is where most field failures start, because a return current that has to detour around a split becomes a loop antenna. At 10 GHz in Dk 3.38, λg is 18.4 mm, so a detour of 4–5 mm is already a quarter wavelength of the return path.

The exception: symmetry is worth more than electrical elegance on thin cores. A 0.2 mm high-frequency core sandwiched between dissimilar copper weights will bow after reflow, and the bow changes the dielectric height, which changes impedance. Balancing copper distribution and putting the high-frequency layers near the centre of the stack is a mechanical decision that protects an electrical one. Stack templates for four, six and eight layers are in high-frequency PCB stack-up design.

Line width is often treated as a free variable that the layout engineer can tune to fit the routing channel. For a controlled-impedance line it is not free: it is fixed by the ratio of width to dielectric height, so once the stack is chosen the width is chosen too. The table below gives the ratio for 50 Ω microstrip on the laminates used most often.

The check: every impedance-controlled net gets its width from this ratio, and the CAM team compensates for etch. Side etch is roughly the copper thickness divided by the etch factor, so at an etch factor of 1.5 a 1 oz foil loses 23 µm per edge: a line drawn at 100 µm finishes at 54 µm at the base, averages 77 µm, and measures 30 % higher resistance than the drawing implies. On 2 oz the same arithmetic eats a 100 µm line completely, which is why the practical fine-line limit for 2 oz copper is about 0.15 mm.

The exception: on a high-Dk material the line becomes narrow enough that the etch tolerance is a real fraction of the width. At Dk 11.2 the 50 Ω line is 0.22 mm on a 0.254 mm core, and ±25 µm is ±11 % of the width — more than the whole impedance budget. High-Dk materials reduce area; they do not reduce the tolerance problem, they move it into the etcher. Width and spacing conventions are compared in trace width and spacing in high-frequency PCB processing.

Crosstalk is set by the ratio of edge-to-edge spacing to dielectric height, and by the parallel length over which the two traces run. The popular 3W rule is a proxy for that ratio; on a 0.1 mm dielectric, 3W is a much weaker requirement than 3h, and on a 1.5 mm dielectric it is stricter than necessary. The numbers below are for microstrip on one dielectric height with a parallel run long enough to matter.

The check: write s/h on the drawing for the nets that carry the sensitive signal, and write the parallel length beside it, because coupling accumulates with length. A pair that runs together for 30 mm couples more than one that crosses at an angle for 3 mm, whatever the spacing says.

The exception: widening a trace does not reduce crosstalk at fixed spacing; it increases the coupling by bringing more copper into the field. The useful levers are spacing, dielectric height and a continuous reference plane. If the channel is too narrow to open the spacing, the answer is a thicker dielectric or a ground trace stitched with vias — not a wider signal line.

The 90° corner rule is the most repeated and least quantified item in the whole list. A right-angle bend adds a small capacitance at the corner, and the discontinuity matters only when its electrical size approaches the rise time. On a 0.254 mm dielectric with 35 µm copper, the corner is roughly one line width across — 0.59 mm on a 4003C stack. At 20 GHz that is about 0.03 λg, well under the etch tolerance of the line itself. Below 20 GHz a 90° corner is a cosmetic issue; above 40 GHz, and in the presence of a wide trace or a thick dielectric, it becomes measurable and a mitred or radiused bend is worth the area.

Intra-pair skew is the item that actually costs yield. The budget comes from the receiver: a 5 ps allowance at Dk 3.38 corresponds to 0.75 mm of length difference, because the signal travels at roughly 150 mm/ns. A single meander that adds 2 mm to one leg of a pair has already spent three times the budget, and no amount of impedance control recovers it.

The exception: matched length is not matched delay when the two legs sit on different layers. A pair that changes layer through two vias accumulates via delay and via stub resonance, and the stub is the bigger term above 20 GHz. Match on the same layer where possible, and if a layer change is unavoidable, keep the stub shorter than 0.5 mm.

The return current of a signal follows the path of least impedance, and which impedance is least depends on frequency. Below a crossover frequency the resistance of the plane dominates and current spreads; above it, inductance dominates and the current crowds directly under the trace. The crossover can be estimated as f ≈ R/(2πL) for the plane geometry.

The practical consequence: above a few hundred kilohertz, and certainly at 10 GHz, the return current is not spread across the plane, it is a narrow band under the trace. At 10 GHz roughly 80 % of it lies within three dielectric heights of the trace centreline — 0.76 mm on a 0.254 mm stack. A plane that looks continuous but is stitched with a slot, a via antipad or a connector cut-out will force that band to detour.

The exception, and the most common error in the original article: multi-point grounding is a low-frequency strategy. On an RF board, splitting a ground into several nets that meet only at a single point creates exactly the loop the current wants to avoid. The correct check is continuity of the reference plane under every high-frequency trace, plus via fences at the board edge and alongside the trace at a spacing below λg/20 — about 0.9 mm at 10 GHz. A 5 mm via pitch is λg/3.7 at that frequency and behaves as an open. The physical basis is in concepts of electricity in PCB.

Decoupling is not a component choice, it is an impedance target. The target is Z = ΔV/ΔI, so a 1.0 V rail that must hold within 5 % while delivering a 10 A transient needs 5 mΩ across the whole frequency band of that transient. Once the target exists, capacitors are selected to fill the band rather than placed by habit.

The check: the target must hold from the regulator’s bandwidth up to the frequency where the on-die capacitance takes over, and every capacitor has a self-resonant frequency above which it is an inductor. A 0.1 µF 0402 with 0.9 nH of mounting inductance self-resonates near 17 MHz, so above 17 MHz it is the mounting, not the capacitance, that sets the impedance. Ten of them in parallel do not fix that; moving them closer to the pins and shortening the via does.

The exception: on a high-frequency board the plane pair itself is a capacitor, and above a few hundred megahertz it is often the only one that matters. What it cannot do is supply charge fast enough if the plane pair is thin and the via count low. The impedance curve, including the capacitor landscape, is worked through in power supply noise on high-frequency PCBs.

“Minimise vias” is directionally right and quantitatively useless. A 1.6 mm through-via in a 1.6 mm board is about 1.3 nH, which is 82 Ω at 10 GHz — a visible discontinuity in a 50 Ω line, and a bigger one in a 100 Ω differential pair where the two vias couple. The larger problem is the unused portion of the barrel, which behaves as a quarter-wave resonator.

The check: for every signal via, record the stub length and the highest frequency on that net. Where the stub is longer than a quarter wavelength at that frequency, the choice is a blind or buried via, back-drilling, or a different layer assignment. Antipad diameter is the second number: enlarging it lowers the via capacitance but raises the risk of a plane void under the trace, and the two effects must be simulated rather than guessed.

The exception: blind and buried vias do not reduce parasitic inductance enough to justify their cost in most designs — they reduce the stub, and that is the real benefit. They also add press cycles, and every additional press cycle adds registration error. On PTFE the aspect ratio limit of about 6:1 constrains the drill diameter long before impedance does. Hole types and their controls are catalogued in special process holes in PCB manufacturing.

Placement is a distance problem measured against wavelength. A decoupling capacitor more than λg/20 away from the pin it serves is electrically somewhere else: at 10 GHz that is 0.9 mm, which is roughly the width of a 0402 land pattern plus its via. The check is therefore a distance in millimetres, not an instruction to place components close.

The second number is the mounting inductance. A capacitor whose loop from pad through via to plane is longer than its own body has a self-resonance set by that loop, and adding capacitance beyond the point where the loop dominates raises the impedance at high frequency instead of lowering it. Two capacitors of different value in parallel create an anti-resonance between their self-resonant frequencies where impedance peaks — a peak that a single value would not have.

The exception: on a receive chain, a filter placed before the LNA protects the noise figure, and its insertion loss is a system budget item, not a parasitic to be minimised. The rule that a filter should be as close as possible to the connector can be wrong when the connector is a launch whose own discontinuity dominates; in that case the filter belongs after a matched transmission section.

Frequency does not generate heat. A 10 W power amplifier dissipates 15 W of heat regardless of its carrier, and the traces carrying the signal dissipate less than 3 W. What the laminate choice changes is the path that heat takes out of the board. The steady-state thermal resistance of a layer is R″ = t/k, and for the same 0.254 mm thickness the families differ by a factor of seven.

The check: compute the vertical resistance of the dielectric under the hottest component, then decide whether heat leaves through copper or through the board. A 0.254 mm layer of RO4003C is thermally equivalent to 143 mm of copper — so the laminate is an insulator and the copper is the heat spreader. Filled via arrays are the mechanism: a 0.2 mm copper-filled via is about 72 K/W, and an array of them under a 5 mm×5 mm pad brings the path down to a few K/W.

The exception: on a low-loss PTFE board, adding thermal vias under an RF line changes the local dielectric environment and the impedance. The vias must be placed under ground pads and outside the field of the transmission line, or modelled. Thermal management of a high-frequency board is therefore an RF layout decision before it is a heat-sink decision; the engineering is set out in high-frequency PCB thermal management.

A design that cannot be measured cannot be accepted. Three numbers define whether the board can be built and proved. The first is the impedance coupon: it must be built on the same stack, the same panel and the same press cycle, because a coupon from another panel is a different experiment. The second is the stencil area ratio for the finest pitch, which must exceed 0.66 — at 0.4 mm pitch that forces a 0.1 mm stencil and non-solder-mask-defined pads, because a 0.18 mm mask bridge between pads cannot be printed. The third is the finest line width, which is 0.15 mm on 2 oz copper for the side-etch reason given in check 4.

The check to write down: for each critical net, name the coupon feature that proves it, and for each fine-pitch device, name the pad definition and the stencil thickness. A design review that ends without those two lists has not finished.

The exception: on a prototype run it is legitimate to accept a coupon-only proof and defer the finished-board TDR. It is not legitimate to describe the coupon result as the product result. The distinction matters when the launch and the via field dominate the measurement, which is exactly the case on a millimetre-wave board. Test methods and their blind spots are compared in testing steps in high-frequency PCB production.

Twelve checks are only useful if each one has an owner and a place to be recorded. The table below is the sheet to attach to the design review, with the number that has to appear beside each line.

Five statements that appear on design review minutes and should not: that wider traces reduce crosstalk (they do not, at fixed spacing); that more layers improve cooling (they add thermal resistance in PTFE); that 90° corners cause reflections at 10 GHz (the corner is smaller than the etch tolerance); that blind vias reduce parasitics enough to be worth their cost (they reduce the stub, and that is the whole benefit); and that multi-point grounding lowers noise on an RF board (it creates the loop). Each of those is a rule of thumb borrowed from a different frequency range.

The key points in high frequency PCB design become usable when each one is written as a number that someone signs: a Df at the highest operating frequency, an impedance budget that adds to less than the window, a plane count derived from the signal layers, a width that follows from the dielectric height, an s/h ratio instead of a 3W rule, a skew budget in picoseconds, a via fence pitch in fractions of a wavelength, a target impedance in milliohms, a stub length against a quarter wave, a decoupling distance in millimetres, a thermal resistance per layer, and a coupon feature per critical net.

Twelve numbers, twelve owners, one page. That page is what separates a design that can be reviewed from a list of things that everyone agrees are important. For routing-level detail on the same board, see six tips for high-frequency PCB routing and addressing EMC in layer-up design.