How to Manufacture Multilayer PCB High-Frequency Boards: The Five Stations That Change

Every published flow for a multilayer board is the same twelve steps, and that is exactly why this question keeps being asked: if the flow is identical, what makes a high-frequency multilayer board different? The answer is not a different flow but five different stations. The oxide step cannot be a black oxide, because PTFE has no polarity for the epoxy to bond to. Lamination runs at one of three temperatures and they cannot be co-cured. Drilling softens rather than cuts. Permanganate desmear does nothing. And hot-air levelling is a thermal shock rather than a finish. This article walks the twelve steps and gives the window, the failure mode and the acceptance check at each of the five that actually change.

The original version of this page answered “how to manufacture multilayer PCB high-frequency boards” with six flow strings: single-sided, double-sided with tin, double-sided with nickel-gold, multilayer with tin, multilayer with hard gold, multilayer with immersion nickel-gold. All six are accurate as far as they go, and none of them mentions the material once. A fabricator could run every one of those sequences on FR-4 and on PTFE and the paper flow would look the same, which is precisely why a buyer reading it learns nothing about what they are paying for.

The useful statement is narrower: the skeleton is identical for every multilayer board, and five stations out of twelve are decided by the laminate rather than by the drawing. Those five are the oxide, the press, the drill, the desmear and the finish. Everything else — imaging, etching, plating, solder mask, electrical test — changes only in its window, not in its nature.

Read down the middle column and the pattern is visible: nothing about the sequence changes, and five of the twelve steps are governed by the fact that PTFE is chemically inert, mechanically soft and thermally a different animal. The rest of this article takes those five in order.

A multilayer build starts with a panel that has to end up the same size after three or four press cycles, and the laminate decides how much of the tolerance the cutting step is allowed to eat. Across a 600 mm panel and a 20 °C swing, a PTFE laminate at 26–31 ppm/°C moves 0.31–0.37 mm, a hydrocarbon at 10–11 ppm moves 0.12–0.13 mm, and FR-4 at 16 ppm moves 0.19 mm. That is why every dimension is called out at 20 ±2 °C rather than at whatever the shop floor happens to be.

Two process rules follow and both are about heat. Laser cutting is excluded on PTFE, because above roughly 400 °C the material decomposes with release of hydrogen fluoride and carbonyl fluoride, and the cut edge is carbonised to the point where nothing will bond to it. Water jet is discouraged rather than forbidden: it cuts cleanly but drives water and garnet into a soft, open edge, which then has to be dried and milled away anyway. What is used is a diamond-coated router or saw, dry, with dust extraction at the source, and the part is roughed 3–5 mm oversize, allowed to relax, then finished.

The practical tolerance set on the router is ±0.1 mm on the finished outline, squareness within 0.1 mm over 300 mm, tooling holes ±0.025 mm and burr under 0.05 mm. Those tooling holes are the datum for every subsequent layer, so a hole that is 0.03 mm out at cutting is 0.03 mm of the layer-to-layer budget already spent. The full tolerance chain is in substrate cutting for high-frequency PCBs.

Inner-layer imaging on a high-frequency multilayer is the least exotic step in the whole build, and it is where most of the impedance error is created. Etching removes copper sideways as well as downwards, so the resist image becomes a trapezoid: the undercut per side is roughly the copper thickness divided by the etch factor. At an etch factor of 1.5 that is 12 µm per side on 0.5 oz, 23 µm on 1 oz and 47 µm on 2 oz.

Two consequences matter for a multilayer high-frequency build. The first is that thin cores are the ones that suffer: a 0.127 mm core carrying a 50 Ω line is narrow to begin with, so a fixed ±25 µm etch tolerance is a much larger fraction of it than of a 1 mm line on a thick core, and the impedance follows. The second is that the compensation belongs in CAM, applied to the drawn image rather than to the finished number, and it has to be stated on the drawing that the widths are finished widths. The full arithmetic is in route width in PCB manufacturing, and the etch variables themselves are in PCB etching.

After AOI the inner layers go to the bonding step. This is the single point where a high-frequency multilayer stops following the FR-4 route.

On FR-4 the copper is given a brown or black oxide so that the epoxy in the prepreg has something to bond to: the treatment grows a rough, polar, high-surface-area copper oxide that reacts with the resin during cure. Peel strength of 1 N/mm and above depends on it, and the whole multilayer stack depends on that peel strength.

PTFE has no polar groups for any resin to react with, and its surface energy is around 18–20 mN/m, which is why nothing sticks to it. Growing oxide on the copper does not help, because the failure is not at the copper-resin interface but at the PTFE-resin interface. The two treatments that do work both change the PTFE itself: sodium naphthalenide in a glyme solvent, which etches the surface and leaves a 1–3 µm micro-porous layer with carbonyl and hydroxyl groups; or a plasma treatment, which does the same job with oxygen and fluorine chemistry and no liquid waste.

The handling rule that goes with either route is that the treated surface has a shelf life measured in hours, not days. A stack that is treated on Friday and pressed on Monday has to be re-treated, and the rework is not visible on the finished board until the thermal cycle testing.

This is the step that most often goes wrong when a mixed stack is quoted from a single flow chart. The three material families cure or fuse at temperatures that do not overlap, and a press cycle has one temperature.

Run all three in one cycle and two things happen. The FR-4 is held above its cure temperature for an hour longer than it needs, which drives out volatiles and embrittles the resin; and the PTFE never reaches the temperature at which FEP flows, so the bond is a mechanical contact rather than a fusion. The result passes electrical test and fails at the first reflow, or passes the first reflow and fails the third.

The correct route for a mixed dielectric board is sequential: press the PTFE sub-assembly at its own temperature with its own bondply, then bond that sub-assembly to the FR-4 layers using a low-flow prepreg or a bondply that cures inside the FR-4 window. Both press cycles spend tolerance, which is why the layer-to-layer registration budget is quoted per press. At roughly ±25 µm per cycle, a four-press stack can accumulate ±0.1 mm of positional error, and a 0.1 mm microvia landing on a 0.25 mm pad has 75 µm of annular ring left to absorb it.

There is a second, quieter cost: PTFE cold-flows under pressure. Thinning the dielectric by 4 % turns a 50.0 Ω line into 48.8 Ω and the change is not recoverable, because there is no cross-linked network to spring back. Starting from a slightly thicker laminate and pressing at the lower end of the pressure window is how that is managed, and the same mechanism is why a PTFE board cannot be re-pressed to fix a registration error. The press window in detail, including void formation and the arithmetic of height against impedance, is in lamination in high-frequency PCBs.

An FR-4 drill cuts glass fibres and epoxy and produces a powder. A PTFE drill pushes a soft, low-friction material that tends to deform rather than shear, and the heat generated at the point softens it further. The failure is smear: a thin film of re-deposited PTFE across the copper target pad, which no permanganate will remove and no electroless copper will plate through.

Acceptance is on the hole wall, not on the hole diameter. Barrel roughness of 25 µm or better, no smear on the target pad under 50× inspection, and no nail-heading (the copper foil pushed into the hole by the drill) beyond the IPC-6012 allowance. All three are drilling artefacts and none of them can be corrected downstream, which is why the drill parameters are qualified per material rather than per board. Laser drilling is a separate subject: PTFE does not absorb 9.3 µm CO₂ output, so microvias in PTFE are drilled with UV or excimer sources at controlled energy, and the debris has to be removed by plasma rather than permanganate. The process detail is in drilling for high-frequency PCBs.

Alkaline permanganate desmear works because it oxidises the epoxy in the drill smear. PTFE is one of the most chemically inert polymers in commercial use and permanganate does not touch it, so the standard desmear line leaves the smear exactly where it was and also leaves the barrel chemically inert for the palladium activator. A board that has been through a normal FR-4 line and then plated will show skip plating or pull-away at the knee, and it will do so on a fraction of the holes rather than all of them, which makes it look like a plating bath problem.

The two routes that work are the same two that work for the oxide: sodium naphthalenide, or plasma. Both remove the smear and functionalise the surface in a single operation, and both have to be qualified by a hole-wall inspection rather than by a bath analysis.

The aspect-ratio ceiling is lower than for FR-4 for two reasons that compound: PTFE requires a dedicated (and slower) desmear, and its Z-axis expansion is 217–237 ppm/°C, so the copper barrel is asked to stretch by 75–82 µm over a 1.6 mm board on the way to reflow. A plating that is 20 µm thick with 20 % elongation survives that; a brittle 15 µm deposit does not. The plating sequence itself is in plating for high-frequency PCBs.

Outer-layer imaging on a multilayer high-frequency board is usually pattern-plated rather than panel-plated, because pattern plating puts copper only where the traces are and therefore keeps the etch short. The cost is that the current density across a panel with very different copper loads is uneven, so trace thickness varies with position, and thickness is half of the impedance equation.

What arrives at the etcher is not what leaves it. A 100 µm image on 1 oz foil with an etch factor of 1.5 finishes at about 54 µm at the base and 77 µm average, which is 30 % more resistance than the nominal width implies; the same image on an outer layer, after 20–25 µm of plating, finishes narrower at the top and thicker in section, so the same nominal width has a different impedance on an inner and an outer layer. That is why impedance coupons are layer-specific, and why a coupon from the inner layer cannot be used to sign off the outer.

The practical control is a flash etch of 0.5–1.0 µm after pattern plating to remove the thin copper between traces without eating the trace itself, and a CAM compensation set to at least the copper thickness on the layers that carry controlled-impedance lines.

Solder mask is specified as a mechanical and chemical barrier, and on a high-frequency board it is also a dielectric sitting directly on top of the transmission line. Its Dk is 3.5–4.2 against 2.2 for PTFE and 3.38 for RO4003C, and a 25 µm layer over a microstrip lowers the impedance of that line by roughly 1–3 Ω relative to the bare coupon. That is not a defect; it is a predictable offset that has to be in the design, and it is one of the reasons a finished board measures lower than its coupon.

The manufacturing problem is adhesion. PTFE at 18–20 mN/m will not wet, so the mask either beads or bonds weakly and lifts at the first reflow. Plasma pre-treatment before mask, plus an ink qualified for low-energy surfaces, plus a cure profile that does not exceed the laminate’s dimensional stability, is the combination that holds. Legend ink is worse: white legend has a Dk of around 6.5, so a legend block printed across an impedance line is a local dielectric change, and the rule on RF layers is to keep legend off the RF traces entirely rather than to accept a small shift. The mask process in detail is in solder mask for high-frequency PCBs.

Hot-air levelling is 250–260 °C for a few seconds, which sounds mild until it is multiplied by the Z-axis expansion of the laminate. On a 1.6 mm PTFE board the 215 K excursion produces about 82 µm of expansion at 237 ppm/°C, and the air knife simultaneously presses the softened dielectric. The result is a barrel that is stretched and a dielectric that is thinner than it was designed to be, which is a permanent impedance shift rather than a cosmetic issue.

For that reason a multilayer high-frequency board is normally finished with ENIG, immersion silver or OSP. ENIG has its own trade-off worth stating: the 3–6 µm nickel layer is 2–5 times the nickel skin depth at 10 GHz (1.33 µm), so at that frequency the current is travelling in nickel, whose surface resistance is about twice copper’s. Immersion silver has no nickel and is the lower-loss choice where soldering is still required; OSP is the lowest-loss and the shortest-lived. The comparison, with the skin depths and the cost per square foot, is in surface treatment for high-frequency PCB production.

A high-frequency multilayer is not more expensive because the flow is longer. It is more expensive because five stations run slower, and one of them runs more than once.

That is why the honest answer to “how many layers can you make” is not a single number. XCE PCB builds 2 to 72 layers on panels up to 600×1200 mm, but a 40-layer PTFE stack is a different commercial proposition from a 40-layer FR-4 one, and the constraints that decide it are the press count, the aspect ratio and the coupon test rather than the drill count.

Before a high-frequency multilayer is released to the floor, these ten items decide whether it will pass:

1. Laminate and bondply part numbers per layer, with Dk and thickness tolerance, not “Rogers”. 2. Which layers are PTFE and which are FR-4, and therefore how many press cycles. 3. Oxide route stated: naphthalenide or plasma, never black oxide on a PTFE face. 4. Finished widths per layer, with the CAM compensation responsibility named. 5. Drill chart by span, with the PTFE parameters called out separately from the FR-4 ones. 6. Desmear route stated, with the ionic cleanliness limit. 7. Aspect ratio per hole, against the 6:1 ceiling and a plating elongation of 20 % or better. 8. Mask type and plasma pre-treatment, plus the legend keep-out on RF lines. 9. Finish chosen against the frequency, not against habit. 10. Coupon design and the impedance window per layer, with the test method named (TDR or VNA) and the sample location at the panel centre and edge.

Ten items, and the ones that get dropped are usually 3, 6 and 10 — the three that cannot be inspected on the finished board. A stack that has been black-oxided, permanganate-desmeared and signed off on a single coupon will look perfect and fail in the field.

The flow for a multilayer high-frequency board is the same twelve steps as any other multilayer, and the value is in knowing which five of them are governed by the material. The oxide has to be naphthalenide or plasma, because PTFE has no polarity and no surface energy for a resin to bond to. Lamination runs at 170–190 °C for FR-4, 190–200 °C for hydrocarbon and 260–300 °C for PTFE with FEP, and those three cannot be co-cured, so a mixed stack is pressed twice and pays registration tolerance twice. Drilling runs slower because the material softens before it shears. Permanganate desmear does nothing to PTFE, which is why the same board plated on an FR-4 line fails at the knee. And hot-air levelling is a thermal shock on a laminate that expands 82 µm across a 1.6 mm board at reflow.

Everything else — imaging, etching, plating, mask, test — is a window rather than a difference. A supplier who cannot describe those five windows in numbers is quoting a flow chart, not a process.

XCE PCB runs both routes in one plant: 2 to 72 layers, panels to 600×1200 mm, impedance held to ±10 % with coupon verification, samples in as fast as 24 hours, inspected to IPC-A-600G and IPC-6015. Send the stack and the drill chart, and the process route comes back itemised per press cycle — request a quote or WhatsApp +86 180 3818 8537. The twelve-step overview this article breaks down is in high-frequency PCB manufacturing process.